R1610C RDC Semiconductor, R1610C Datasheet - Page 78

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
the Divisor Latch Access bit via the Line Control Register (LCR). The programmer can also read the contents of the
Line Control Register. The read capability simplifies system programming and eliminates the need for separate
storage in system memory of the line characteristics. The detailed contents of each bit of LCR register is as follows:
R
16.6
78
Register Offset:
Register Name:
Reset Value
15
Bit
2
1
0
7
6
D
D
The system programmer specifies the format of the asynchronous data communications exchange and sets
Enabled
14
Name
RCVR
DLAB
Reset
Reset
XMIT
FIFO
FIFO
FIFO
C
Line Control Register
C
SB
13
®
®
:
Attribute
R
R
I
I
S
S
C
C
R/W
R/W
R/W
R/W
RW
86h
UART0 Line Control Register
XX00h
D
D
12
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
n
n
XMIT FIFO Reset. Writing a 1 to FCR0[2] clears all bytes in the XMIT FIFO and
resets its counter logic to 0. The shift register is not cleared. The 1 that is written to
this bit position is self-clearing.
RCVR FIFO Reset.
Writing a 1 to FCR0[1] clears all bytes in the RCVR FIFO and resets its counter logic
to 0. The shift register is not cleared. The 1 that is written to this bit position is
self-clearing.
FIFO Enable.
Writing a 1 to FCR0 enables both the XMIT and RCVR FIFO. Resetting FCR0[0] will
clear all bytes in both FIFO.
When changing from FIFO Mode to NS16450 Mode and vice versa, data is
automatically cleared from the FIFOs.
This bit must be a 1 when written to other FCR bits or they will not be programmed.
Divisor Latch Access bit.
Set 1: To access the Divisor Latches of the Baud Generator during a Read or Write
Set 0: To access the Receiver Buffer, the Transmitter Holding Register, or the
Break Control bit.
It causes a break condition to be transmitted to the receiving UART.
Set 1: the serial output (SOUT) is forced to the Spacing (logic 0) state.
Set 0: the Break is disabled.
The Break Control bit acts only on SOUT and has no effect on the transmitter logic.
Note: This feature enables the CPU to alert a terminal in a computer communications
i
i
c
c
a
a
t
t
i
i
o
o
n
n
10
1.Load an all Os, pad character, in response to THRE.
2.Set break after the next THRE.
system. If the following sequence is followed, no erroneous or extraneous
characters will be transmitted because of the break.
Interrupt Enable Register
operation.
9
8
DLAB
7
Break
Set
6
Description
Parity
Stick
5
EPS
4
Fast Ethernet RISC Processor
PEN
3
STB
2
WSL1 WSL0
1
R1610C
October 27, 2003
0
Final Version 1.5
Data Sheet