R1610C RDC Semiconductor, R1610C Datasheet - Page 84

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
as follows:
A. The receive data available interrupt will be issued to the CPU when the FIFO has reached its programmed
B. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
C. The receiver line status interrupt (IIR=06), as before, has higher priority than the received data available
D. The data ready bit (LSR [0]) is set as soon as a character is transferred from the shift register to the RCVR
A. A FIFO timeout interrupt will occur, if the following conditions exist:
B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to
C. When a timeout interrupt has occurred: It is cleared and the timer reset when the CPU reads one character from
D. When a timeout interrupt has not occurred: The timeout timer is reset after a new character is received or after
R
16.12
115200
230400
460860
19200
38400
57600
Rates
1200
2400
4800
9600
84
This will cause a maximum character received to interrupt issued delay of 160 ms at 300 BAUD with a 12-bit
the baud rate).
the RCVR FIFO.
the CPU reads the RCVR FIFO.
─at least one character is in the FIFO.
─the most recent serial character received was longer than 4 continuous character time (if 2 stop bits are
─the most recent CPU read of the FIFO was longer than 4 continuous character time.
trigger level; it will be cleared as soon as the FIFO drops below its programmed trigger level.
interrupt, it is cleared when the FIFO drops below the trigger level.
(IIR=04) interrupt.
FIFO. It is reset when the FIFO is empty.
D
D
programmed the second one is included in this time delay).
character.
When the RCVR FIFO and receiver interrupts are enabled (FCR [0]=1, IER [0]=1), RCVR interrupt will occur
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts will occur as follows:
C
FIFO Interrupt Mode Operation
C
DLM
0Fh
07h
03h
01h
0h
0h
0h
0h
0h
0h
®
®
R
R
I
I
S
S
C
C
DLL
A1h
D1h
E8h
7Ah
0Ah
42h
F4h
51h
29h
14h
D
D
S
S
P
P
C
C
o
o
m
m
m
m
u
u
n
n
234375
468750
114329
i
i
c
c
38422
57870
19211
a
a
Baud
1200
2400
4798
9606
t
t
i
i
o
o
n
n
Dev.(%)
0.04
0.06
0.06
0.06
0.76
1.73
1.71
0.5
0
0
DLM
0Ah
14h
05h
02h
01h
0h
0h
0h
0h
0h
DLL
2Ch
8Bh
A3h
6Dh
1Bh
0Eh
58h
16h
46h
36h
115741
231481
446428
19171
57339
38344
Baud
1200
2400
4800
9601
Fast Ethernet RISC Processor
Dev.(%)
0.15
0.15
0.45
0.47
0.47
3.13
0
0
0
0
R1610C
October 27, 2003
Final Version 1.5
Data Sheet