R1610C RDC Semiconductor, R1610C Datasheet - Page 130

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
● Read Cycle (100 MHz)
General Timing Requirements
Read Cycle Timing Responses
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on SD_CLK unless otherwise noted. All output test
R
22.3
No.
10
12
13
14
15
16
17
18
24
25
26
27
28
29
59
66
67
130
11
1
2
6
9
D
General Timing Responses
D
conditions are with C
a. Equal loading on referenced pins. T1 wait states should be inserted to increase hold time.
b. This parameter applies to the WR_n signal.
c. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Symbol
t
t
t
t
t
t
t
t
t
CXCSX
CHCSX
t
t
t
t
CHCSV
t
t
t
CLCSV
t
t
t
t
t
t
AVCH
RHAV
RHDX
C
DVCL
CLDX
CLAX
CHLH
RLRH
CLRH
RHLH
AVRL
CPU Bus
CHLL
AVLL
LLAX
CLAZ
AZRL
CLRL
C
LHLL
®
®
Data in Setup
Data in Hold
Address Hold
ALE Active Delay
ALE Width
ALE Inactive Delay
SAD Address Valid to ALE Low
SAD Address Hold from ALE Inactive
SAD Address Valid to Clock High
SAD Address Float Delay
PCS_n Active Delay
PCS_n Hold from Command Inactive
PCS_n Inactive Delay
SAD Address Float to RD_n Active
RD_n Active Delay
RD_n Pulse Width
RD_n Inactive Delay
RD_n Inactive to ALE High
RD_n Inactive to SAD Address Active
RD_n High to Data Hold on SAD Bus
SAD Address Valid to RD_n Low
SD_CLK High to UCS_n Valid
R
R
I
I
S
S
C
C
D
D
S
S
P
P
C
Parameter
C
L
o
o
m
m
= 50 pF. For switching tests, V
m
m
u
u
n
n
(c)
i
i
c
c
a
a
t
t
i
i
o
o
n
n
Description
(a)
(a)
(a)
(a)
(a)
(c)
(a)
IL
= 0.45 V and V
4.4 (T1+no wait)
2T (0 wait)
Min.
IH
0.4
0.8
2.8
4.5
1T
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2
3
3
8
7
5
3
6
0
= 2.4 V, except at X1 where V
Fast Ethernet RISC Processor
Preliminary
100 MHz
9.2 (T1+wait)
0.8+T1 wait
2T+T3 wait
Max.
1.5T
2.7
1.2
3.5
14
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---
---
---
---
---
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0
6
R1610C
IH
October 27, 2003
= V
Final Version 1.5
CC
Data Sheet
– 0.5 V.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns