R1610C RDC Semiconductor, R1610C Datasheet - Page 14

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
● MII Interface
R
14
PIN No.
109
108
107
106
105
116
112
115
114
117
110
111
D
25
26
27
28
29
30
31
D
C
C
®
®
TXD1_0/PFEREQ0
DTR1_n/SBWSEL
TXD1_3/PDIVD0
TXD1_2/PDIVD1
TXD1_1/PDIVD2
TXEN1/CLKJMP
R
R
CTS1_n/TMS
DSR1_n/TCK
RTS1_n/TDO
DCD1_n/TDI
I
I
S
S
C
C
RXD1_3
RXD1_2
RXD1_1
RXD1_0
Symbol
D
D
SOUT1
RXDV1
S
RXC1
S
TXC1
SIN1
P
P
C
C
o
o
m
m
m
m
u
u
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
I/O/PU
I/O/PU
I/O/PD
I/O/PD
O/UP
Type
I/PU
I/PU
I/PU
I/PD
I/PD
I/PD
I/PD
O
I
SAD10: The combination pin with Address and Data. It is for
slower device bus.
SIN1: Serial Data Input.
SOUT1: Serial Data Output. This pin cannot be pulled low.
RTS1_n: Request To Send.
TDO: JTAG test data output pin
DTR1_n: Data Terminal Ready.
SBWSEL is to decide the SAD bus width when the RST_n pin
goes from low to high. If SBWSEL is with a pull-low resistor
(4.7k ohm), the SAD bus width is 8 bits and 16550’s Port 0 is
active. Otherwise the SAD bus width is 16 bits and 16550 Port 0
is inactive.
CTS1_n: Clear To Send.
JTAG Test mode select pin
DSR1_n: Data Set Ready.
TCK: JTAG test clock input pin
DCD1_n: Carry Sense Detection.
TDI: JTAG test data input pin
Four parallel transmit data lines. This data is synchronized to the
assertion of the TXC signal and is latched by the external PHY
on the rising edge of the TXC signal.
PDIVD [2:0] & PFEREQ [0] are hardware configured pins during
reset for Multiple PLL. (See chapter.5)
PDIVD [2:0]: Multiple selection.
PFEREQ [0]: Input clock range selection.
This pin functions as transmit enable. It indicates that a
transmission is active on the MII port to an external PHY device.
CLKJMP: It is a hardware-configured pin, used to select the
CLKOUTA output from internal Multiple PLL or X1. When high,
the CLKOUTA is from Multiple-PLL. When low, the CLKOUTA is
from X1.
Supports the transmit clock supplied by the external PMD
device. This clock should always be active.
Supports the receive clock supplied by the external PMD device.
This clock should always be active.
Four parallel receive data lines. This data is driven by an
external PHY that the media is attached and should be
synchronized with the RXC signal.
Data valid is asserted by an external PHY when the received
data is present on the RXD1 [3:0] lines and is de-asserted at the
Fast Ethernet RISC Processor
Description
R1610C
October 27, 2003
Final Version 1.5
Data Sheet