R1610C RDC Semiconductor, R1610C Datasheet - Page 61

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
SD_CLK. It takes a minimum of four clocks before the DMA cycle is initiated by the Bus Interface. The DMA request
is cleared four clocks before the end of the DMA cycle. And no DMA acknowledge is provided, since the
chip-selects (PCSx_n) can be programmed to be active for a given block of memory or I/O space, and the DMA
source and destination address registers can be programmed to point to the same given block.
Source-Synchronized Transfer figure shows the typical source-synchronized transfer which provides the source
Data Sheet
Final Version 1.5
October 27, 2003
R
14.2
Register Offset:
Register Name:
Reset Value
15-4
Register Offset:
Register Name:
Reset Value
15-0 DSA[15:0]
3-0
15
Bit
15
Bit
D
D
External DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the falling edge of
DMA transfer can be either source- or destination-synchronized, and it can also be unsynchronized. The
DSA[19:16]
14
14
C
Name
External Requests
C
Name
Rsvd
13
13
®
®
:
:
R
R
I
I
S
S
Attribute
C
Attribute
C
D2h (DMA1)
DMA1 Source Address High Register
──
D0h (DMA1)
DMA1 Source Address Low Register
──
D
D
12
12
S
S
R/W
R/W
P
P
RO
C
C
o
o
m
m
m
m
u
u
11
11
n
n
i
i
c
c
a
a
t
t
Reserved
High DMA 1 Source Address.
These bits are mapped to A[19:16] during a DMA transfer when the source
address is in memory space or I/O space. If the source address is in I/O space
(64Kbytes), these bits must be programmed to 0000b.
Low DMA 1 Source Address.
These bits are mapped to A[15:0] during a DMA transfer.
The value of DSA[19:0] will be incremented or decremented by 2 or 1 after each
DMA transfer.
i
i
o
o
n
n
10
10
Reserved
9
9
8
8
DSA [15:0]
7
7
6
6
Description
Description
5
5
4
4
Fast Ethernet RISC Processor
3
3
DSA [19:16]
2
2
1
1
R1610C
0
0
61