R1610C RDC Semiconductor, R1610C Datasheet - Page 40

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R1610C

Manufacturer Part Number
R1610C
Description
High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
Manufacturer
RDC Semiconductor
Datasheet
R
Peripheral Chip Size table:
FFAAh bit8-6
R
14-8
40
Register Offset:
Register Name:
Reset Value
1-0
15
Bit
15
1
7
6
5
4
3
2
D
D
000
001
010
100
011
14
Name
R[1:0]
Rsvd
Rsvd
Rsvd
C
PR4
C
MS
R4
R3
R2
13
®
®
:
PCS0
BASE
BASE
BASE
BASE
BASE
Attribute
R
R
I
I
S
S
C
C
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
A8h
PCS_n Auxiliary Register
──
D
D
12
S
S
P
P
C
C
o
o
Reserved
m
m
m
m
u
u
11
n
n
Reserved
Reserved
Reserved
Memory or IO space selector. This bit determines whether the PCS_n pins are active
during memory bus cycle or IO bus cycle.
Set 1: PCS_n active for memory cycle. Set 0: PCS_n active for IO cycle.
See bit[1:0] in the A4h register.
See bit[1:0]
See bit[1:0].
Ready Mode. This bit only applies to the PCS6_n – PCS5_n chip selects.
Set 1: external ready is ignored.
Set 0: external ready is required.
Bit 4-3 and Bit 1-0: R4, R3, R1, R0, Wait-State Values.
R4, R3, R1, and R0 determine the number of wait states inserted into T3 of the
PCS5_n – PCS6_n access.
i
i
c
c
a
a
t
t
i
i
o
o
n
n
PCS1
BASE+256
BASE+512
BASE+1024
BASE+2048
BASE+4096
10
1,
1,
0,
0,
0,
0,
1,
1,
1,
1,
1,
1,
9
0,
1,
1,
1,
1,
1,
0,
0,
0,
1,
1,
1,
8
PCS2
BASE+512
BASE+1024
BASE+2048
BASE+4096
BASE+8192
0,
1,
0,
0,
1,
1,
0,
1,
1,
0,
0,
1,
Rsvd
7
0
0
0
1
0
1
1
0
1
0
1
1
MS
6
--
--
--
--
--
--
--
--
--
--
--
--
Description
PCS3
BASE+768
BASE+1536
BASE+3072
BASE+6144
BASE+12288
PR4
5
60
210
9
15
25
40
80
100
125
150
180
255
R4
4
Fast Ethernet RISC Processor
R3
3
BASE+10240
PCS5
BASE+1280
BASE+2560
BASE+5120
BASE+20480
R2
2
R1
1
R1610C
BASE+12288
BASE+24576
PCS6
BASE+1536
BASE+3072
BASE+6144
October 27, 2003
R0
0
Final Version 1.5
Data Sheet

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