R1610C RDC Semiconductor, R1610C Datasheet - Page 82

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
peripheral device) to the CPU. In addition to this current-state information, four bits of the MODEM Status Register
provide change information. These bits are set to logic 1 whenever a control input from the MODEM changes its
state. They are reset to logic 0 whenever the CPU reads the MODEM Status Register. The contents of the MSR
register are described as below.
R
16.9
82
Register Offset:
Register Name:
Reset Value
15
Bit
1
0
7
6
D
D
This Modem Status Register (MSR) provides the current state of the control lines from the MODEM (or
14
Name
DCD
C
Modem Status Register
C
OE
DR
RI
13
®
®
:
Attribute
R
R
I
I
S
S
C
C
R/W
R/W
R/W
R/W
8C
UART0 MODEM Status Register
XXX0h
D
D
12
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
n
n
In the FIFO mode, this error is associated with the particular character in the FIFO it
applies to. This error is revealed to the CPU when its associated character is at the
top of the FIFO.
Overrun Error indicator.
This bit indicates that the data in the Receiver Buffer Register were not read by the
CPU before the next character was transferred into the Receiver Buffer Register,
thereby destroying the previous character.
Set 1: Indicate OE indicator is set to logic 1 upon detection of an overrun condition.
Set 0: Automatic reset to 0 whenever the CPU reads the contents of the Line Status
If the data in the FIFO mode continue to fill the FIFO beyond the trigger level, an
overrun error will occur only after the FIFO is full and the next character has been
completely received in the shift register. OE is indicated to the CPU as soon as it
happens. The character in the shift register is overwritten, but it is not transferred to
the FIFO.
Data Ready indicator.
Set 1: Indicate whenever a complete incoming character has been received and
Set 0: Automatic set to 0 by reading all of the data in the Receiver Buffer Register or
Data Carrier Detect.
This bit is the complement of the Data Carrier Detect (DCD_n) input.
If bit 4 (Loop Bit) of the MCR is set to 1, this bit is equivalent to OUT2 in the MCR.
Ring Indicator.
This bit is the complement of the Ring Indicator (RI_n) input.
If bit 4 (Loop Bit) of the MCR is set to 1, this bit is equivalent to OUT1 in the MCR.
i
i
c
c
a
a
t
t
i
i
o
o
n
n
10
Register.
Register.
transferred into the Receiver Buffer Register or the FIFO.
the FIFO.
9
8
DCD
7
RI
6
Description
DSR
5
CTS
4
Fast Ethernet RISC Processor
DDCD
3
TERI
2
DDSR DCTS
1
R1610C
October 27, 2003
0
Final Version 1.5
Data Sheet