R1610C RDC Semiconductor, R1610C Datasheet - Page 75

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
individually activate the interrupt output signal (UARTINT). It is possible to totally disable the interrupt system by
resetting bits 0 through 3 of the Interrupt Enable Register. Similarly, setting the relative bit of the IER register to 1
will enable the selected interrupt(s). Disabling an interrupt prevents it from being indicated as being active in the IIR
and from activating the UARTINT output signal. All other system functions operate in their normal manners,
including the setting of the Line Status and MODEM Status Registers. The details of each bit for the IER are
described as below:
Data Sheet
Final Version 1.5
October 27, 2003
R
16.3
16.4
Register Offset:
Register Name:
Reset Value
the UART prioritizes interrupts into four levels and records these in the Interrupt Identification Register (IIR). The
four levels of interrupt conditions in priority order are Receiver Line Status, Received Data Ready, Transmitter
Holding Register Empty, and MODEM Status.
interrupt to the CPU. While this CPU access is occurring, the UART records new interrupts, but does not change
its current indication until the access is complete. The details of each bit of Interrupt Identification Register are
described as below.
7-4
15
Bit
3
2
1
0
D
D
This Interrupt Enable Register (IER) enables the four types of UART interrupts. Each interrupt can
This is a read only register. In order to provide minimum software overhead during data character transfers,
When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority pending
14
ETHREI
ERDAI
ERLSI
Name
C
EMSI
Interrupt Enable Register
Rsvd
Interrupt Identification Register
C
13
®
®
:
R
R
I
I
Attribute
S
S
C
C
82h
UART0 Interrupt Enable Register
XX00h
D
D
12
R/W
R/W
R/W
R/W
RO
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
n
n
i
i
c
c
a
a
Reserved and always 0.
The MODEM Status Interrupt bit.
Set to 1 to enable the MODEM Status Interrupt.
The Enable Receiver Line Status Interrupt bit.
Set to 1 to enable the Receiver Line Status Interrupt.
The Enable Transmitter Holding Register Empty Interrupt bit.
Set to 1 to enable the Transmitter Holding Register Empty Interrupt.
The Enable Received Data Interrupt bit.
Set to 1 to enable the Received Data Available Interrupt (and timeout interrupts in
the FIFO mode).
t
t
i
i
o
o
n
n
10
9
8
7
0
6
0
Description
5
0
4
0
Fast Ethernet RISC Processor
BMSI ERLSI
3
2
ETHREI
1
R1610C
ERDAI
0
75