R1610C RDC Semiconductor, R1610C Datasheet - Page 48

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
R
15-8
48
Register Offset:
Register Name:
Reset Value
2-0
2-0
15
Bit
6
5
4
3
7
6
5
4
3
D
D
PR[2:0]
PR[2:0]
14
SFNM
SFNM
Name
Rsvd
MSK
ETM
MSK
C
ELS
LTM
ELS
LTM
C
13
®
®
:
Attribute
R
R
I
I
S
S
C
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
38h
INT0 Control Register
000Fh
D
D
12
Reserved
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
n
n
Special Fully Nested Mode.
Set 1: Enable the special fully nested mode of INT1
Edge/Level Select
Set 1: falling edge / Low level trigger
Set 0: rising edge /High level trigger
Level-Triggered Mode.
Set 1: An Interrupt is triggered by level.
Set 0: An interrupt is triggered by edge.
Mask.
Set 1: Mask the interrupt source of INT1.
Set 0: Enable the INT1 interrupt.
Interrupt Priority.
These bit settings for priority selections are the same as those of bit 2-0 for the 44h
register.
Reserved
Edge trigger mode enabled. When this bit is set and bit 4 is cleared to 0, an interrupt
is triggered by the edge going from low to high. The low to high edge will be latched
(one level) till this interrupt is serviced.
Special Fully Nested Mode.
Set 1: Enable the special fully nested mode of INT0
Edge/Level Select
Set 1: Falling edge/Low level trigger.
Set 0 : Rising edge/High level trigger.
Level-Triggered Mode.
Set 1: An Interrupt is triggered by level.
Set 0: An interrupt is triggered by edge.
Mask.
Set 1: Mask the interrupt source of INT0.
Set 0: Enable the INT0 interrupt.
Interrupt Priority.
These bit settings for priority selections are the same as those of bit 2-0 for the 44h
register.
i
i
c
c
a
a
t
t
i
i
o
o
n
n
10
9
8
ETM
7
SFNM
6
Description
ELS
5
LTM
4
Fast Ethernet RISC Processor
MSK
3
PR2
2
PR1
1
R1610C
PR0
October 27, 2003
0
Final Version 1.5
Data Sheet