R1610C RDC Semiconductor, R1610C Datasheet - Page 24

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R1610C

Manufacturer Part Number
R1610C
Description
High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
Manufacturer
RDC Semiconductor
Datasheet
R
7.
R
7.1 Legacy Peripheral Registers (Base Address FF00h)
Offset
(HEX)
Peripheral Control Block Relocation Register (FEh). After reset, the default Legacy Peripheral Control Block offset
is located at FF00h in I/O space, the SDRAM Control Register is located at FE00h in I/O space, and Ethernet
Control Register is located at FD00h and FE00h in I/O space.
descriptions will be arranged on the related Block Unit.
24
DA
CA
FE
EA
D8
D6
D4
D2
D0
C8
C6
C4
C2
C0
AA
F8
F6
F4
F2
E6
E4
E2
A8
A4
A0
7A
88
86
84
82
80
D
Peripheral Register List
D
The Peripheral Control Block can be mapped into either Memory or I/O space by programming the
The following table lists are all the definitions of the Peripheral Control Block Registers, and the detailed
Register Name
Peripheral Control Block Relocation
Register
Processor Extended ID Register
Reset Configuration Register
Processor Release Level Register
Auxiliary configuration Register
Bus Control Register
Watchdog Timer Control Register
Enable RCU Register
Clock Prescaler Register
DMA 1 Control Register
DMA 1 Transfer Count Register
DMA 1 Destination Address High
Register
DMA 1 Destination Address Low
Register
DMA 1 Source Address High Register
DMA 1 Source Address Low Register
DMA 0 Control Register
DMA 0 Transfer Count Register
DMA 0 Destination Address High
Register
DMA 0 Destination Address Low
Register
DMA 0 Source Address High Register
DMA 0 Source Address Low Register
Chip Size Multiplier Register
PCS_n Auxiliary Register
Peripheral Chip Select Register 0
Upper Memory Chip Select Register
PIO Data 1 Register
(See 7.2)
(See 7.2)
(See 7.2)
(See 7.2)
(See 7.2)
C
C
®
®
R
R
I
I
S
S
C
C
D
D
S
S
P
P
C
C
o
o
m
m
m
m
u
u
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
Page
28
29
31
28
37
34
71
43
43
59
61
61
61
62
62
57
57
58
58
58
59
42
40
39
38
25
25
25
25
25
88
(HEX)
Offset
5C
3C
2C
5E
5A
52
44
40
3A
38
36
32
30
2E
2A
28
26
24
70
66
62
60
58
56
54
50
42
34
22
18
16
Register Name
PIO Mode 0 Register
Timer 2 Mode/Control Register
Timer 2 Maxcount Compare A Register
Timer 2 Count Register
Timer 1 Mode/Control Register
Timer 1 Maxcount Compare B Register
Timer 1 Maxcount Compare A Register
Timer 1 Count Register
Timer 0 Mode/Control Register
Timer 0 Maxcount Compare B Register
Timer 0 Maxcount Compare A Register
Timer 0 Count Register
Serial Port 0 interrupt control register
Serial port 1 interrupt control register
MAC Interrupt Control Register
INT2 Control Register
INT1 Control Register
INT0 Control Register
DMA1/INT6 Interrupt Control Register
DMA0/INT5 Interrupt Control Register
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
Interrupt In-service Register
Interrupt Priority Mask Register
Interrupt Mask Register
Interrupt Poll Status Register
Interrupt Poll Register
Interrupt End-of-Interrupt
(See 7.2)
(See 7.2)
Fast Ethernet RISC Processor
R1610C
October 27, 2003
Final Version 1.5
Data Sheet
Page
90
69
70
70
67
69
68
68
65
66
66
66
46
46
47
48
48
49
50
50
51
51
52
52
53
54
54
55
55
25
25

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