R1610C RDC Semiconductor, R1610C Datasheet - Page 143

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
24.
Data Sheet
Final Version 1.5
October 27, 2003
R
The above instruction timings represent the minimum execution time in clock cycles for each instruction. The
timings given are based on the following assumptions:
1. The opcode, along with data or displacement required for execution, has been prefetched and resided in the
instruction queue at the time needed.
2. No wait states or bus HOLDs occur.
3. All word -data are located on even-address boundaries.
4. One RISC micro operation (uOP) maps one cycle (according to the pipeline stages described below), except
the following case:
4.1 Memory read uOP need 6 cycles for bus.
4.2 Memory push uOP need 1 cycle if it has no previous Memory push uOP, and 5 cycles if it has previous
Memory push or Memory Write uOP.
4.3 MUL uOP and DIV of ALU function uOP for 8 bits operation need both 8 cycles, for 16 bits operation need
both 16 cycles.
4.4 All jumps, calls, ret and loopXX instructions required to fetch the next instruction for the destination address
(Unconditional Fetch uOP) will need 9 cycles.
Note: op_r: operand read stage, EA: Calculate Effective Address stage, Idle: Bus Idle stage, T0..T3: Bus T0..T3
stage,
Access: Access data from cache memory stage.
Pipeline stages for Memory push uOP after Memory push uOP (another 5 cycles):
(2
Pipeline stages for unconditional fetch:
(next uOP) Fetch
Fetch
Fetch
nd
D
R1610C Execution Timing
D
uOP) Fetch
Decode
Decode
C
C
Pipeline stages for Memory read uOP(6 cycles):
Fetch
®
®
Pipeline Stages for single micro operation(one cycle):
These 9 cycles caused branch penalty
R
R
Decode
I
Decode
I
S
S
EA
EA
C
C
Decode
D
D
S
S
P
P
Fetch
Fetch
C
C
o
o
m
m
Access
m
m
u
u
Access
EA
n
n
EA
i
i
c
c
a
a
t
t
i
i
EA
o
o
n
n
Decode
Decode
Access
Idle
Access
Idle
Access
op_r
EA
Access
Access
T0
T0
will be flushed
Idle
Access
Access
Access
ALU
T1
pipeline stall
T1
T0
Bus Cycle
Access
T2
Access
T2
WB
WB
T1
Access
T3
T3
Access
T2
(For ALU function uOP)
(For Memory function uOP)
Idle
Fetch
Fetch
T3
Idle
WB
Fast Ethernet RISC Processor
T0
Decode
WB
T0
T1
(1
T1
following stages..
st
(Fetch uOP)
T2
Memory push uOP)
T2
T3
R1610C
T3
WB
.
(New uOP)
WB
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