cx29503 Mindspeed Technologies, cx29503 Datasheet

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cx29503

Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
Preliminary Information
This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.
CX29503
Broadband Access Multiplexer (BAM)
The CX29503 Broadband Access Multiplexer (BAM) is a highly integrated, cost-effective,
monolithic device which performs the mapping, multiplexing, demultiplexing, and framing
of three STS-1, AU-3, DS3, E3, or one AU-4 inputs to any valid combination of 84 DS1 or
63 E1 signals. The CX29503 may be used as a SONET/SDH-to-PDH mapper supporting all
standard mappings at 51 Mbps, 2 Mbps, and 1.5 Mbps rates, or it may be used as a PDH
muldem only. It generates and terminates all Virtual Tributary (VT) and Virtual Container
(VC) path overhead. It includes three embedded DS3/E3 framers, three M13/E13
MUX/DEMUX blocks with G.747 support, and 84 embedded DS1 framers and 63
embedded E1 framers. Other features include standards-compliant alarm indicators,
status monitoring and error counters for all supported tributaries, and an embedded
Command and Status Processor (CSP) that offloads major network maintenance activities
from the host processor.
(CX28500) and the STS-12/STM-4 SONET/SDH Framer/Multiplexer device (CX29610),
allows equipment suppliers to develop single, high-density, software-configurable system
solutions for datacom and IP path terminating applications supporting both North
American and European transmission standards. The high level of integration drives down
per-port framer cost and dramatically reduces board space requirements. A complete
STS-12/STM-4 system channelized down to DS1/E1 for an IP HDLC packet processing
solution requires only seven devices from Mindspeed.
The CX29503 supports current ANSI, ETSI, ITU, and Telcordia standards with embedded,
enhanced network alarming and maintenance features that reduce real-time requirements
on the host processor. Physical layer support is provided for alarm generation and
detection, error monitoring, and data link maintenance.
Functional Block Diagram
29503-DSH-002-B
Interface
SI-Bus
The CX29503, in conjunction with Mindspeed's 1,024-channel HDLC Controller device
DS3/E3 Serial
Interface
SI-Bus
Level
MUX
Top-
SI-Bus
I/F
STS-1 to
DS3/E3
Mapper
DS3/E3
Framer
Unchannelized STS-1
VC-11/VC-12
TUG-2/3 to
VT1.5/2.0
STS-1 to
MUX
M13/E13
Unchannelized DS3/E3
DEMUX
DS1/VC-11, and E1/VC-12
MUX
DS1/VT1.5, E1/VT2.0,
Mindspeed Technologies™
28xVT1.5/VC-11
21xVT2.0/VC-12
Tributary Mapper
Termination/
Generation
Overhead
Preliminary Information
28xDS1
Framers
21xE1
Processor Interface
To Host Processor
E-Bus Interface
(Optional)
E-Bus
Command
and Status
Processor
Time Slot
Interface
Module
SLICE 1
SLICE 2
Bus
SLICE 3
Overhead
Payload
TSB
100702_010a
TSB
Distinguishing Features
• Capacity
• Supports two types of line interfaces:
• System Interface
• Supports the following multiplexing
• Supports the following mapping
• Embedded PDH framers including:
– Three STS-1 or TUG-3 or DS3 or
– SONET Interleave Bus (SI-Bus)
– DS3/E3 serial interfaces for a
– Supports three serial Time Slot
modes:
– PDH
– SONET/SDH
modes:
– SONET/PDH
– SDH/PDH
– DS3 to VC-3
– 3 x DS3/E3 framers
– 21 x DS2/E2 framers
– 84 x DS1/E1/J1 framers
E3 line-side inputs
interfaces for a parallel data bus
connection to the SONET/SDH
multiplexer devices at the
STS-1/TUG-3 data rates
connection to Line Interface Units
(LIU)
Bus (TSB) interfaces for a
connection to high-density HDLC
controller devices. Time slots can
be configured to transmit DS3/E3,
DS1/E1/J1, STS-1, or VT1.5
payloads
• M13
• E13
• G.747
• STS-1/VT1.5
• STS-1/VT2.0
• TUG-3/VC-11
• TUG-3/VC-12
• DS3 to STS-1
• E3 to STS-1
• DS1 to VT1.5
• J1 to VT1.5
• E1 to VT2.0
• E3 to VC-3
• DS1 to VC-11
• J1 to VC-11
• E1 to VC-12
October
2004

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