cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 108

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Clock Sources and Clock Configurations
4.3
4.3.1
Table 4-2. DS3 Clock Sources and Configuration Bits in SI-Bus Interface Mode
4-4
DS3 Receive Framer Line
Clock (LINECLK)
DS3 Transmit Framer Line
Clock (m13_clk_txlineo)
FOOTNOTE:
(1)
upl3txclkset[1:0] is located in the M13/E13 System Control register
TXE3_CLKSEL is located in the Clock Configuration register
Description
SI-Bus Interface Mode
DS3/E3 Clock and Data Configurations (SI-Bus Interface Mode)
In the SI-Bus Interface mode, the line side of the device is connected to an external
SONET/SDH MUX device via the SI-Bus.
required in this mode. This mode is enabled by setting the CK_SRC[1:0] pins to 0 × 0
or 0 × 1.
Table 4-1. SI-Bus Clock Sources in SI-Bus Interface Mode
The MUXes shown in
timing) and DS3/E3 modes (DS3 or E3).
settings for the DS3 and E3 modes, respectively.
CK_SRC[1:0] pins are set to 0
If the data path is unchannelized STS-1, then the line clocks (m13_clk_txtlineo and
LINECLK) listed in
DS3/E3 framer can be disabled by clearing the FrEnable bit in the DS3/E3 Framer
Control register (See
SIB_RXHSCLK
SIB_TXHSCLK
SIB_RXCLK
SIB_TXCLK
Pin Description
44.736
44.736
(MHz)
Freq.
Mindspeed Technologies™
System or Looped
System
Looped
Preliminary Information
Tables 4-2
Section
Timing Mode
Figure 4-1
Freq. (MHz)
51.84
51.84
19.44
19.44
(Section
8.4.1).
×
and
0 or 0
are configured based on the Timing (system or loop
(Section
4-3
8.8).
System or Looped
System or Looped
System or Looped
System or Looped
×
are not needed. Furthermore, the complete
1.
Tables 4-2
Timing Mode
SONET Block
CLK_TXDS3
8.4.1).
Table 4-1
LINECLK
Source
Clock
Tables 4-2
and
shows the clocking sources
4-3
TXE3_CLKSEL = Don't Care
and
show the configuration
External SONET/SDH MUX
External SONET/SDH MUX
External SONET/SDH MUX
External SONET/SDH MUX
upl3txclkset[1:0] = 0 × 1
upl3txclkset[1:0] = 0 × 0
TXE3_CLKSEL = 0 × 0
Configuration Bits
4-3
Clock Source
(CX29610)
(CX29610)
(CX29610)
(CX29610)
assume the
CX29503 Data Sheet
—
29503-DSH-002-B
(1)