cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 44

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cx29503

Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
Product Description
Table 1-8. Pin Definitions(2 of 6)
1-18
TLINECLK[2:0]
CK_SRC [1:0]
CLK_TXDS3
CLK_TXDS1
TXPOS[2:0]
TXNEG[2:0]
CLK_TXE3
CLK_TXE1
TRISTATE
RESET_N
CLK_1HZ
Symbol
Reset
low
low
low
low
Z
(1)
Type
IO12
IPU
O2
O2
O2
I
I
I
I
I
I
Mindspeed Technologies™
(2)
Serial Line Side Interface
Preliminary Information
Signal
Clock and Control
Name
Reset—This is the active-low, system reset signal. This
signal is used as power-up reset.
Output Three-State Control—When driven high, all output
pins are driven into high impedance state.
DS3 Transmit Reference Clock— Reference clock for the
transmit direction. This should be 44.736 MHz ± 20 ppm,
50% ± 5% duty cycle clock. Must be greater than 43.1 MHz
in E3 line side mode to drive the TSB clock (see
E3 Transmit Reference Clock—Reference clock for the
transmit direction. This should be 34.368 MHz ± 20 ppm,
50% ± 5% duty cycle clock.
DS1 Transmit Reference Clock—DS1 reference clock for
the transmit direction. This should be a jitter-free clock at
1.544 MHz.
E1 Transmit Reference Clock—E1 reference clock for the
transmit direction. This should be a jitter-free clock at
2.048 MHz.
One-second Timer—If configured as input, this 1 Hz signal
is used to latch error counter values. If configured as
output, the internal 1 Hz time base is brought out on this
pin. This pin is configured as an input by default.
System Interface Select—External pins required to select a
valid system interface (SI-Bus or DS3/E3 Serial) for
CX29503 data and clock operations. A 0x0 or 0x1 signal
selects the SI-Bus as the system interface. A 0x2 or 0x3
selects the DS3/E3 Serial interface as the data source and
allows selection between CLK_TXE3 and CLK_TXDS3 as
the clock source using TXE3_CLKSEL in the Clock
Configuration Register (see
Transmit Line Clock—Provides external indication of the
transmit clock. It is used to clock out the line data signals.
D3/E3 TX Positive Line Data or NRZ Line Data—In Bipolar
mode, positive data is transmitted on this line. For NRZ
mode, NRZ data is transmitted on this line. This signal can
be aligned to either the positive or negative edge of
TLINECK.
D3/E3 TX Negative Line Data or Unused—In Bipolar mode,
negative data is transmitted on this line. In NRZ mode, this
pin is unused and driven low. This signal can be aligned to
either the positive or negative edge of TLINECK.
Name and Function
Section
8.8).
CX29503 Data Sheet
29503-DSH-002-B
Figure
4-3).

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