cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 55

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
2.5.1.1
Figure 2-5. SI-Bus Transmit Signal Relationship
29503-DSH-002-B
from Slave1
from Slave2
from Slave3
TxData[7:0]
TxData[7:0]
TxData[7:0]
TxStart
TxClk
Transmit Interface
The master device generates TxHSClk, TxClk, and TxStart signals to control the slave
devices. The slave devices respond with TxData and TxPrty in their appropriate time
slots. The master device samples TxData and TxPrty on the rising edge of TxClk. The
master device provides TxStart synchronously with the rising edge of TxClk. The data
relationships are shown below in
A1 octet position (the first octet of the STS frame) on clock edge 2 after the TxStart
signal is provided (edge 1). The master device samples data on every TxClk edge,
with 2,430 clock edges defining the 3 interleaved STS-1 frames. Each slave device
responds on every third TxClk edge and is three-stated during the intervening 2 TxClk
cycles. Each slave has a predetermined time slot in which it is expected to respond
relative to the rising edge of the TxStart signal. The slave device does not have to
generate the correct Transport Overhead, but needs to insert dummy data on these
clock edges. The master device generates the correct Transport Overhead. The content
of the Path Overhead positions is dependent on the master/slave implementations. The
TxPrty signal is not shown but should follow the same relationship as TxData. A
multichannel capable slave does not have to three-state the data bus between channels
and can drive interleaved data continuously onto the bus.
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Mindspeed Technologies™
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Preliminary Information
A1
2
A1
Figure
2-5. The master device expects to sample the
A1
A2
A2
A2
Functional Description
100702_013
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