cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 259

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x5242—Counter Interrupt Status Register
The Counter Interrupt Status register contains status information about active interrupts needing service from
the controller. This register needs to be read by the controller upon receiving a counter interrupt to determine the
source of the interrupt. The interrupt indications are active-high in the register and can be set even if the
interrupt is not enabled. The bits in this register are cleared when the register is read.
Value after reset:
Direction:
Value after enable:
EXZCtrltr
XdgrCtrltr
LCVCtrltr
FEBECtrltr
PthCtrltr
FerrCtrltr
PdgrCtrltr
ParCtrltr
29503-DSH-002-B
EXZCtrltr
7
XdgrCtrltr
00(h)
Read only
00(h)
Excessive Zeros (EXZ) Counter Interrupt—Set high on EXZ error counter roll-over or
saturation. The EXZ Counter Interrupt Enable bit, EXZCtrlE bit in the Counter Interrupt
Control register, determines the status of the counter (roll-over or saturation).
X-bits Disagreement Counter Interrupt—Set high if the X disagreement counter has either
rolled over or is saturated. The Disagreement Counter Interrupt Enable bit (XdgrCtrIE)
determines the status of the counter (roll-over or saturation). In E3-G.751 mode, this bit is low
because there are no X-bits.
LCV Counter Interrupt—Set high on an LCV error counter roll-over or saturation. The LCV
Counter Interrupt Enable bit (LCVCtrIE) determines the status of the counter (roll-over or
saturation).
FEBE Event Counter Interrupt—Set high if the FEBE event counter has either rolled over or is
saturated. The FEBE Event Counter Interrupt Enable bit determines the status of the counter
(roll-over or saturation). In E3-G.751 mode and any DS3-M13/M23 modes, this bit is low
because there is no FEBE/REI event defined.
Path Parity Error Counter Interrupt—In DS3 mode, set high if the path parity error counter has
either rolled over or is saturated. The Path Parity Error Counter Interrupt Enable bit determines
the status of the counter (roll-over or saturation). In DS3-M13/M23 and E3-G.751 modes, this
bit is low because there is no path parity check.
Frame Error Counter Interrupt—Set high when the frame error counter has either rolled over
or is saturated. The Frame Error Counter Interrupt Enable determines the status of the counter
(roll-over or saturation).
P-Bits Disagreement Counter Interrupt—Set high if the P-bits disagreement counter has either
rolled over or is saturated. The Disagreement Counter Interrupt Enable bit determines the
status of the counter (roll-over or saturation). In E3-G.751 mode, this bit is low because there
is no parity disagreement counter defined.
Parity Error Counter Interrupt—Set high if the parity error counter has either rolled over or is
saturated. The Parity Error Counter Interrupt Enable bit determines the status of the counter
(roll-over or saturation). In E3-G.751 mode, this bit is low because there is no parity/BIP-8
check defined.
6
LCVCtrltr
5
Mindspeed Technologies™
FEBECtrltr
Preliminary Information
4
PthCtrltr
3
FerrCtrltr
2
PdgrCtrltr
1
Register Description
ParCtrltr
0
8
-
129