cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 141
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cx29503
Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
1.CX29503.pdf
(388 pages)
- Current page: 141 of 388
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CX29503 Data Sheet
0x01F3—TSB FIFO Interrupt Enable Register (Used for DS1 Diagnostics)
These interrupts are only used for diagnostic testing. If the system clock driving the TSB interface fails, the
Transmit FIFOs will underflow and the Receive FIFOs will overflow. However, the TSB block will not respond
to reads of this register because of the failed system clock.
TXPFIFO OVRFL
TXPFIFO UNDRFL
RXPFIFO OVRFL
RXPFIFO UNDRFL
TXOFIFO OVRFL
TXOFIFO UNDRFL
RXOFIFO OVRFL
RXOFIFO UNDRFL
0x01F4—Overflow Tx Payload FIFO Number Status Register (Used for Diagnostics)
Num[7:0]
29503-DSH-002-B
RXOFIFO
UNDRFL
Num[7]
7
7
RXOFIFO
Interrupt enable for Transmit Payload FIFO Overflow. Do not enable this interrupt because the
FIFO will tend to run full during normal operation.
Interrupt enable for Transmit Payload FIFO Underflow. This interrupt should only be enabled
for DS1 operation. In other modes of operation, unused payload transmit FIFOs will stay
empty and generate continuous interrupts.
Interrupt enable for Receive Payload FIFO Overflow.
Interrupt enable for Receive Payload FIFO Underflow. Do not enable this interrupt because the
FIFO will tend to run empty during normal operation.
Interrupt enable for Transmit Overhead FIFO Overflow. Do not enable this interrupt because
the FIFO will tend to run full during normal operation.
Interrupt enable for Transmit Overhead FIFO Underflow. This interrupt should only be
enabled for DS1 operation. In other modes of operation, unused overhead transmit FIFOs will
stay empty and generate continuous interrupts.
Interrupt enable for Receive Overhead FIFO Overflow.
Interrupt enable for Receive Overhead FIFO Underflow. Do not enable this interrupt because
the FIFO will tend to run empty during normal operation.
A register value of 0x00 indicates no Transmit Payload Transmit FIFO Overflow errors.
Register values of 0x01–0x1C indicate which one of the 28 Transmit Payload FIFOs
overflowed. This register only reports the first FIFO to overflow. The subsequent overflow of
another FIFO will not be reported until this register is cleared.
Num[6]
OVRFL
6
6
TXOFIFO
UNDRFL
Num[5]
5
5
Mindspeed Technologies™
TXOFIFO
Num[4]
OVRFL
Preliminary Information
4
4
RXPFIFO
UNDRFL
Num[3]
3
3
RXPFIFO
Num[2]
OVRFL
2
2
TXPFIFO
UNDRFL
Num[1]
1
1
Register Description
TXPFIFO
OVRFL
Num[0]
0
0
8
-
11
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