cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 252

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x522B—REXTCK Control Register
The REXTCK Control register provides for the marking of different fields through the REXTCK signal. On the
CX29503, the REXTCK signal is an output from the DS3/E3 block to the TSB block. This signal is only used to
clock the data for the terminal data link channel (DL) that is transferred on the RXDAT signal.
The DL field should be disabled from being presented on RXGAPCK interface in the Receive Overhead
Control register [addr: 22C].
Default after reset:
Direction:
Modification:
ExtReserved/GC
ExtDL/NR
ExtFEBE/A
ExtCP/TM
ExtFEAC/PD/Stf
ExtAIC/Cj/TR
ExtFrm
AllRxExt
8-122
ExtReserved/GC
7
00(h)
Read/Write
Static
External Reserved C bits/GC byte—Must be cleared on the CX29503.
In DS3-C Bit Parity mode, clearing this bit disables the presentation of reserved C bits (C12,
C2, C6, C7) through the REXTCK signal. In DS3-M13/M23 and E3-G.751 modes, this bit is
ignored.
External Data Link/NR byte—Can be set or cleared on the CX29503.
This bit enables presentation of data link data through the REXTCK signal. The bits are output
exactly as received, i.e., the HDLC circuit is bypassed. In DS3-C Bit Parity mode, this bit
enables presentation of C5 bits through the TSB interface. In E3-G.751 mode, this bit enables
presentation of N-bit through the TSB interface. In DS3-M13/M23, this bit is ignored.
External FEBE/REI/A-bit—Must be cleared on the CX29503.
This bit enables presentation of FEBE field in DS3-C Bit Parity mode through the REXTCK
signal. In E3-G.751 mode, set to enable presentation of A-bit through REXTCK signal. In
DS3-M13/M23 mode, this bit is ignored.
External Path Parity/Timing Marker/SSM—Must be cleared on the CX29503.
This bit enables presentation of the CP field in DS3-C Bit Parity mode through the REXTCK
signal. In DS3-M13/M23 and E3-G.751 modes, this bit is ignored.
External FEAC/Payload Dependent/Multiframe Indicator/Stuff Opportunity bits—Must be
cleared on the CX29503. This bit enables presentation of the FEAC channel in DS3-C Bit
Parity mode or stuff opportunity bits in DS3 M13/M23 and in E3-G.751 modes through the
REXTCK signal.
External AIC/Justification Control/Trail Trace—Must be cleared on the CX29503.
In DS3-C Bit Parity mode, this bit enables presentation of the application identification
channel through REXTCK signal. In DS3-M13/M23 and E3-G.751 modes, set this bit to
enable presentation of the justification control bits through the REXTCK signal.
External Framing fields—Must be cleared on the CX29503. In DS3 modes, this bit enables
presentation of M, F, X, and P bits through the REXTCK signal. In E3-G.751 mode, set this bit
to enable presentation of FAS field through the REXTCK signal.
All Received data is External—Must be cleared on the CX29503. This bit enables presentation
of the complete frame, i.e., payload and overhead bits, through the REXTCK signal. This bit is
available in all framing modes. When this bit is set, it overrides the rest of the bits in this
register. Presentation of overhead bits through the RXGAPCK signal or through the
microprocessor interface in parallel to REXTCK is determined by the Receive Overhead
Control register and by the RxDLEn bit in the Receive Data Link Control register.
ExtDL/NR
6
ExtFEBE/A
5
Mindspeed Technologies™
Preliminary Information
ExtCP/TM
4
ExtFEAC/PD/Stf
3
ExtAIC/Cj/TR
2
ExtFrm
1
CX29503 Data Sheet
29503-DSH-002-B
AllRxExt
0