cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 167

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x15—External Data Link Time Slot (DL3_TS)
DL3_TS works in conjunction with the DL3_BIT register [addr: 016] to access the overhead FDL/Sa4 data
from the TSB overhead channel. The data is configured using TS[0], ODD/EVEN, and DL3_BIT[4:0]. The data
link interface to the TSB is enabled with DL3EN.
DL3EN
ODD/EVEN
TS[0]
29503-DSH-002-B
DL3EN
7
Enable External Data Link—An active-high enables data insertion from the TSB overhead
channel.
Odd/Even Frame Select—The external data link is programmed to source and sink data bits
during all frames, or odd or even frames only. In E1 mode, the CX29503 supports the passing
of Sa data that is contained in odd frames. In T1 mode, ODD/EVEN is ignored.
External Data Link Time Slot Select—If set, then Sa/FDL data is not passed to or from the
TSB overhead bus. If cleared, either Sa data (in E1 mode) or ESF FDL data (in T1 mode) is
passed to and from the TSB overhead bus. The Sa data (Sa 4, Sa5, Sa6, Sa7, or Sa8) selection
is made with DL3_BIT[4:0] in the DL3_BIT [addr: 0x16].
ODD
6
Reserved bits should be written to 0.
0 = external data link to/from TSB overhead channel is inactive
1 = external data link to/from TSB overhead channel is active
Table 8-9. Odd/Even Frame Selection
Table 8-10. External Data Link Time Slot Selection
ODD
TS[0]
0
0
1
1
0
1
EVEN
5
Pass Sa or FDL data to and from the TSB overhead bus
Sa and FDL data not passed
Mindspeed Technologies™
EVEN
0
1
0
1
RESERVED
Preliminary Information
4
None; not supported on the CX29503
Even frames only, not supported on CX29503
Sa4, Sa5, Sa6, Sa7, or Sa8 data
All frames; not supported on the CX29503
RESERVED
3
RESERVED
Data
Frame Select
2
RESERVED
1
Register Description
TS[0]
0
8
-
37