cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 60

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Functional Description
2.6.1
2.6.1.1
2.6.1.2
2.6.1.3
2-12
SONET/SDH Mapper/MUX Receiver
This section describes the functionality of the SONET/SDH Mapper/MUX receiver.
The receiver terminology relates to the line side.
SI-Bus Receiver Interface
SONET/SDH Mapper/MUX receiver interfaces to the line side via the SI-Bus. STS-1
or TUG-3 frames are transported over the SI-Bus from the higher-level MUX device.
The SI-Bus Receiver Interface block is the receiver’s physical interface to the SI-Bus.
It strobes receiver control/data from the SI-Bus and generates the internal control and
byte-wide data bus to be used by the receive side. Control and data are strobed on the
falling edge of the 19.44 MHz SI-Bus receiver clock.
STS-1/TUG-3 SPE Extraction Control
The STS-1/TUG-3 Synchronous Payload Envelope (SPE) extraction control performs
pointer interpretation which locates and processes the H1/H2 pointer bytes and locates
the first byte in the SPE envelope. It counts the SPE bytes and columns so that it
provides a point of reference to the DS3/E3 Demapping function, VT extraction
control, and TSB Interface blocks. In cases where there is a TU-3 in the SPE payload,
this block provides the additional pointer interpretation required for this level. This
block detects AIS-P, New Data Flags (NDFs), new pointers without NDFs, and count
positive and negative pointer justification operations as well as provide the current
pointer value.
DS3/E3 Demapping Function
The DS3/E3 Demapping function demaps an asynchronously mapped DS3/E3 signal
from the payload capacity of an L3 signal residing on the receive side byte-wide data
bus.
The DS3/E3 Demapping function writes 8 bytes of data and 8 bytes of I-bit mask to an
8 × 16 barrier FIFO at a 6.48 MHz rate. The DS3/E3 demapper reads from the FIFO
and serializes the data and I-bit mask to two 51.84 MHz bit streams where DS3/E3
bits are identified by the I-bit mask stream. This I-bit mask stream is the data enable
used by the DS3/E3 smoothing block.
The DS3/E3 Demapping function is implemented with a barrier FIFO so that the data
transfer between the enabled 19.44 MHz clock domain and the 51.84 MHz clock
domain does not rely on a known phase relationship between the 2 domains. The
FIFO’s read/write pointers have a stride of 4 address locations. This stride of 4 is
established through a hardware reset or a software control bit (soft reset).
Mindspeed Technologies™
Preliminary Information
CX29503 Data Sheet
29503-DSH-002-B