cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 360

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x8020—HDLC Controller Status (HDLC_STAT)
Hdlc_Abort:
CRC_Err:
Rx_Ovflw:
Shrt_Msg:
Tx_Len_Full:
Rx_Len_Avl:
Reset State
0x8021—HDLC Transmit Message Length (HDLC_TX_LEN)
When configured to N, indicates that N + 1 bytes of data are to be transmitted. (Does not include CRC bytes and
Frame Patterns.)
Reset State
0x8022—HDLC Received Message Length (HDLC_RX_LEN)
Indicates the number of valid data packets received. (Does not include CRC bytes and Frame Patterns.)
Reset State
0x8023—Parallel Interface Control (PAR_IF_CTL)
Delay[2:0]
Reset State
8-230
Rx_Len[7]
Tx_Len[7]
Reserved
Reserved
7
7
7
7
Tx_Len[6]
Rx_Len[6]
Reserved
Reserved
Indicates an idle pattern 0xFF was detected. This bit is a clear-on-read type.
Indicates that the CRC did not check. This bit is a clear-on-read type.
An overflow condition has occurred on Rx FIFO. This bit is a clear-on-read type.
Indicates that two bytes of the HDLC packet was received. This bit is a clear-on-read type.
Length FIFO (not Data FIFO) on Tx-path (CSP to TSB) is full
Length FIFO (not Data FIFO) on Rx-path (TSB to CSP) is available
00000000
00000000
00000000
Specify number of clocks to delay DTACK before sending to host processor
00000011
6
6
6
6
Rx_Len_Avl
Tx_Len [5]
Rx_Len [5]
Reserved
5
5
5
5
Mindspeed Technologies™
Tx_Len_Full
Tx_Len [4]
Rx_Len [4]
Reserved
Preliminary Information
4
4
4
4
Tx_Len [3]
Rx_Len [3]
Shrt_Msg
Reserved
3
3
3
3
Tx_Len [2]
Rx_Len [2]
Rx_Ovflw
Delay[2]
2
2
2
2
Tx_Len [1]
Rx_Len [1]
Delay [1]
CRC_Err
1
1
1
1
CX29503 Data Sheet
29503-DSH-002-B
Hdlc_Abort
Tx_Len [0]
Rx_Len [0]
Delay [0]
0
0
0
0