cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 242

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x5223—Alarm End Interrupt Enable Register
Writing a one to an IER bit allows that specific interrupt source to activate its respective ISR bit in the Alarm
End Interrupt Status register [addr: 244], set the appropriate bit in the IRR [addr: 241], and report the interrupt
to the Global Control and Status block. If cleared, each IER bit allows that source to activate its respective ISR
bit, but prevents activation of the IRR bit and reporting the interrupt to the Global Control and Status block.
Default after reset:
Direction:
Modification:
LOSEndIE
IdleEndIE
YelEndIE
AISEndIE
OOFEndIE
8-112
Reserved
7
Reserved
00(h)
Read/Write
Dynamic
Enable LOS End Interrupt in all modes.
Enable Idle Interrupt End Interrupt in DS3 mode. This bit has no effect in the E3-G.751 mode.
Enable Yellow Alarm End Interrupt in all modes.
Enable AIS End Interrupt in all modes.
Enable OOF End Interrupt in all modes.
6
NOTE:
Reserved
5
Mindspeed Technologies™
Reserved bits in the Enable and Control registers must be set to 0.
LOSEndIE
Preliminary Information
4
IdleEndIE
3
YelEndIE
2
AISEndIE
1
CX29503 Data Sheet
29503-DSH-002-B
OOFEndIE
0