cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 144

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x01FC—TSB Module Operation
Reset Value
TSYNC_IO
16 x E1
CLEAR E3
CLEAR DS3
CLEAR STS-1
TSBUS
CSPBW
0x01FE—Framer Set (FS) Configuration Register 1
8-14
CSPBW
FS4[1]
7
7
(41 Overhead TSB time slots allocated for CSP and TSB_TSYNCI from a system-side
device.)
Configures the choice of the Transmit Synchronization signal. When set, indicates TSB
provides TSB_TSYNCO to a system-side device. When cleared, indicates TSB receives
TSB_TSYNCI from a system-side device. The setting also determines if the internal sync
signal sent to the DS1/E1 framer is based on TSB_TSYNCO or TSB_TSYNCI.
Selects/deselects the DS1/E1 framers as the TSB module line-side source for mapping of 16
E1 signals. This bit overrides any selection in Framer Set Configuration Register 1 or 2.
Selects/deselects the DS3/E3 framer as the TSB module line-side source for mapping of an
unchannelized E3 signal. This bit overrides any selection in the Framer Set Configuration
Register 1 or 2.
Selects/deselects the DS3/E3 framer as the TSB module line-side source for mapping of an
unchannelized DS3 signal. This bit overrides any selection in Framer Set Configuration
Register 1 or 2.
Selects/deselects SONET STS-1 mapper as TSB module line-side source for mapping an
unchannelized STS-1 signal. This bit overrides any selection in Framer Set Configuration
Register 1 or 2.
When set, configures the TSB system-side pins for TSB mode. This bit must always be set in
the CX29503.
When set, 13 Overhead TSB time slots are allocated for CSP messages. When cleared, 41
Overhead TSB time slots are allocated. The selection of 41 Overhead TSB time slots is valid
only if no SONET/SDH Z7/K4 bits are received from the SONET block or transmitted to the
SONET block. The DrpK4 bit in RXVTCTL (see
receives the Z7/K4 bits from the SONET block. The InsK4 bit in TXVTCTL2 (see
Section
DrpK4 and InsK4 bits must be disabled for all 28 tributaries to allocate 41 time slots for the
CSP (i.e., CSPBW = 0). The default value of CSPBW is 0 (use 41 for CSP).
0x40
TSBUS
FS4[0]
6
6
8.6.1) controls whether the TSB transmits the Z7/K4 bits to the SONET block. The
CLEAR STS-1
FS3[1]
5
5
Mindspeed Technologies™
CLEAR DS3
FS3[0]
Preliminary Information
4
4
CLEAR E3
FS2[1]
3
3
Section
FS2[0]
8.6.2) controls whether the TSB
2
—
2
16 x E1
FS1[1]
1
1
CX29503 Data Sheet
29503-DSH-002-B
TSYNC_IO
FS1[0]
0
0