cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 262

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x5248—Transmit Data Link FEAC Interrupt Status Register (ISR)
An ISR bit is latched active (high) whenever its corresponding interrupt source reports an interrupt event. If the
corresponding interrupt enable is active (high), each interrupt event forces the TxDLFEACltr bit in the IRR
[addr: 241] to active (high) and an interrupt event is reported in real time to the Global Control and Status block.
If the associated interrupt enable is inactive (low), the interrupt event is not reported to the Global Control and
Status block and the TxDLFEACltr bit is not set in the IRR.
Value after reset:
Direction:
Value after enable:
Bit[7] is undefined
TxFEACItr
TxFull
TxMsg
TxUR
TxNE
TxEmpty
8-132
—
7
Reserved
03(h)
Read only
03(h)
Transmit FEAC Channel Ready—In DS3-C Bit Parity mode, set high indicating that the
transmitter is ready for a new byte to be written to the Transmit FEAC Channel Byte register.
When working in FEAC single mode, this happens after every code word transmission start.
When working in FEAC repetitive mode, this happens after the transmitter has started sending
the code word 10 consecutive times for the first time. In DS3-M13/M23 and E3-G.751 modes,
this bit should be ignored. The associated interrupt is enabled in the Feature 3 Control register
[addr: 226] and cleared when this register is read.
Transmit data link FIFO Full—Set when the transmit FIFO contains 128 bytes. Cleared when
there are less than 128 bytes in the transmit FIFO, i.e., this bit is high and the first byte is read.
No interrupt is linked to this bit.
Transmit Data Link Message Transmitted—Set when the final bit of the closing flag of a
message is transmitted. The associated interrupt is enabled in the Transmit Data Link Control
register [addr: 22D] and cleared when this register is read.
Transmit data link Underrun error —Set when the transmit FIFO buffer is empty and the
transmit circuit tries to read another byte from it, i.e., the microprocessor does not meet the
requirements and does not fill the FIFO buffer properly. The associated interrupt is enabled in
the Transmit Data Link Control register [addr: 22D] and cleared when this register is read.
Transmit data link Near-Empty event—Set when TxNEThr bytes or less are left in the FIFO.
Cleared when the number of bytes in the FIFO is greater than TxNEThr. The associated
interrupt is enabled in Transmit Data Link Control register [addr: 22D].
Transmit data link FIFO is Empty—Set when the FIFO is empty, i.e., the last byte is read from
it. Cleared when set and the first write by the microprocessor (after being empty) is done. No
interrupt is linked to this bit.
6
TxFEACltr
5
Mindspeed Technologies™
Preliminary Information
TxFull
4
TxMsg
3
TxUR
2
TxNE
1
CX29503 Data Sheet
29503-DSH-002-B
TxEmpty
0