cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 45

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
Table 1-8. Pin Definitions(3 of 6)
29503-DSH-002-B
SIB_RXSTRT [2:0]
SIB_TXDAT[7:0]
RLINECLK[2:0]
SIB_RXHSCLK
SIB_TXHSCLK
SIB_TXSTRT
SIB_TXPRTY
RXPOS[2:0]
RXNEG[2:0]
SIB_RXCLK
SIB_TXCLK
RXCKI[2:0]
VCO[2:0]
Symbol
Reset
low
low
low
—
—
—
—
—
—
—
—
—
—
(1)
Type
O2
O2
O2
I
I
I
I
I
I
I
I
I
I
Mindspeed Technologies™
(2)
Preliminary Information
Signal
Name
SI-Bus Interface
—
—
—
—
—
—
—
—
—
—
—
—
—
DS3/E3 Line Clock—Clock signal derived from received
data. This should be 44.736 MHz for DS3, 34.368 MHz for
E3.
DS3/E3 Dejittered Clock—This signal is to be used in DS3/
E3/STS-1 Line Interface mode. It is used to clock output of
the internal DS3/E3/STS-1 dejitter FIFO. If unused, tie to
ground.
DS3/E3 Phase Difference Signal—This signal is used by an
external VCO to dejitter the derived line clock.
DS3/E3 Positive Data or NRZ Data—In Bipolar mode,
positive data is received via this pin. In NRZ mode, NRZ
data in input on this pin. Inputs are sampled on the
programmable edge of RLINECLK.
DS3/E3 Negative Data or LCV Data—In Bipolar mode,
negative data is received via this pin. In NRZ mode, line
code violations are input on this pin. Inputs are sampled on
the programmable edge of RLINECLK.
SI-Bus High-Speed Transmit Clock—Internal DS3/VT
payload clocks are generated based on this 51.84 MHz
clock.
SI-Bus Transmit Clock—This clock is used to time all
transmit signals from each mapper/MUX block to the
SONET/SDH MUX device. The nominal clock frequency is
19.44 MHz.
SI-Bus Transmit Frame signal—This signal is provided by
the SONET/SDH MUX device. It indicates start of frame.
This signal is sampled on the falling edge of SIBTXCLK.
SI-Bus Transmit Data—This bus carries the transmit data
from mapper/MUX blocks to the SONET/SDH MUX device.
The data is aligned to the falling edge of SIBTXCLK.
SI-Bus Transmit Data Parity Bit—This bit serves as the odd
parity bit calculated over SIBTXDAT[7:0]. The bit is aligned
to the falling edge of SIBTXCLK.
SI-Bus High Speed Receive Clock—Internal DS3/VT
payload clocks are generated based on this 51.84 MHz
clock.
SI-Bus Receive Clock—This clock is used to time all receive
signals from the SONET/SDH MUX to the mapper/MUX
blocks. The nominal clock frequency is 19.44 MHz.
SI-Bus Receive Frame signal—This signal is provided by
the SONET/SDH MUX. It indicates start of frame. This
signal is sampled on the falling edge of SIBRXCLK.
Name and Function
1
-
19