cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 263

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x524B—Receive Data Link Interrupt Status Register (ISR)
An ISR bit is latched active (high) whenever its corresponding interrupt source reports an interrupt event. If the
corresponding interrupt enable is active (high), each interrupt event forces the RxDLltr bit in the IRR
[addr: 241] to active (high) and an interrupt event is reported in real-time to the Global Control and Status
block.
Value after reset:
Direction:
Value after enable:
RxGoodBlk
RxOVR
RxMsg
RxNF
RxBlk
StatByte
29503-DSH-002-B
Reserved
7
Reserved
Bits 0, 5—undefined; bits 1–4, 6, 7—00(h)
Read only
Bits 0, 5—undefined; bits 1–4, 6, 7—00(h)
Received Good Block indication—Defines the type of status byte. Set for status with length
type in it (a good block (a1) or a2 blocks). Cleared for status with error type in it—bad, errored
block (b block). No interrupt is linked to this bit.
Receive Data Link Overrun Error—Set when the receive FIFO is full and another byte is
received from the line and should be written into the FIFO (and it is not already set). Cleared if
it was set and there are no more unread complete blocks left in the FIFO (this is determined by
the RxBlk bit in this register). The associated interrupt is enabled in the Receive Data Link
Control register [addr: 231].
Receive Data Link FIFO Contains a Message—Set when another status byte of a correct-end-
of-message or an incorrect-end-of-message (including aborted message) is written into the
FIFO. The associated interrupt is enabled in the Receive Data Link Control register
[addr: 231]. Cleared when this register is read.
Receive Data Link Near-Full Event—Set when the number of bytes in the receive FIFO equals
or exceeds the programmable threshold written in the RxNFThr register (and it is not already
set). Cleared if it was set and there are no more unread complete blocks left in the FIFO (this is
determined by the RxBlk bit in this register). The associated interrupt is enabled in the Receive
Data Link Control register [addr: 231].
Receive Data Link FIFO Contains Complete Blocks—Set when there are one or more
complete data blocks in the receive FIFO. Cleared when the last data byte of the last complete
block is read from the FIFO. No interrupt is linked to this bit.
Byte Type Indication—Set when the next byte to be read from the receive FIFO is a status byte.
Clear when the next byte to be read is a data byte. When there is no complete block in the
FIFO, i.e., the RxBlk bit in this register is clear, this bit is undefined. No interrupt is linked to
this bit.
6
If the associated interrupt enable is inactive (low), the interrupt event is not reported
to the Global Control and Status block and the RxDLltr bit is not set in the IRR.
RxGoodBlk
5
Mindspeed Technologies™
RxOVR
Preliminary Information
4
RxMsg
3
RxNF
2
RxBlk
1
Register Description
StatByte
0
8
-
133