cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 102

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Parallel Microprocessor Interface
3.3
Figure 3-1. Top-Level Interrupt Structure
3-2
MUX/DEMUX
DS1/E1 Framer Interrupt
1-Second
Framers
SONET/
DS1/E1
DS3/E3
Mapper
TS Bus
Framer
Timer
SDH
(28)
M13
(0x0004–0x0007)
Status Registers
28
1
Interrupt and Control Signals
. .
The INTR_N output pin is an active-low, open-drain output which provides a common
interrupt request for all of the interrupt sources in the device.
Figure 3-1
controlled by 2 interface registers:
The CSP off-loads the host processor and performs the majority, if not all, of the
interrupt processing. The details depend on the software functional partitioning
between the CSP and the host processor.
Rx
Tx
DS1/E1 Framer Interrupt
. .
Top-Level Interrupt Enable register—a 1 in a given bit of this register enables the
corresponding interrupt, a 0 (initial condition) disables it.
Top-Level Interrupt Status register—events are latched into this register whether
the corresponding interrupt enable bit is enabled or not. The processor must read
this register to clear all the latched bits.
Top-Level Interrupt Status
(0x0008–0x000B)
Enable Registers
Register (0x000A)
shows the top-level interrupt structure within the CX29503. Interrupts are
Mindspeed Technologies™
Preliminary Information
Top-Level Interrupt Enable
Int_Gen
Register (0x0003)
Interrupt Control Reg. (0x8010)
Interrupt
Source
Priority
(0–15)
Level
INT_1
INT_2
Vector
Table
ISR
INT_3
Int_Enb
to ISR Routine
MCSM Jump
CSP
CX29503 Data Sheet
29503-DSH-002-B
INTR_N pin
100702_030