cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 157

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
8.3.2.2
An ISR bit is latched active (high) whenever its corresponding interrupt source reports an interrupt event. The
processor reads the ISR to clear all latched ISR bits. If the corresponding interrupt enable is active (high), each
interrupt event forces the associated IRR bit active (high). Interrupt sources fall into the following two
categories:
If the associated interrupt enable is active (high), an interrupt event is reported in real time to the Global Control
and Status block. If the associated interrupt enable is inactive (low), the interrupt event is not reported to the
Global Control and Status block and the event bit is not set in the IRR. The interrupt status is latched and held in
the ISR according to the selected latching mode [LATCH; addr: 046].
Table 8-7. Interrupt Status Register (ISR) Summary
29503-DSH-002-B
The rising-edge source reports an interrupt event when the status changes from an inactive to active state.
Unless specifically noted otherwise, all ISR bits are rising-edge sources.
The dual-edge source reports an interrupt event when the status changes from inactive to active (rising edge),
or from active to inactive (falling edge). The processor must read the associated real-time status to determine
which edge occurred.
Bit
0
1
2
3
4
5
6
7
RESERVED
RESERVED
RESERVED
ALARM1
RMYEL
RLOS
RLOF
RYEL
ISR7
RAIS
004
Interrupt Status Registers
RESERVED
RESERVED
RESERVED
RESERVED
ALARM2
LOOPDN
ONESEC
LOOPUP
ISR6
005
—
RESERVED
RESERVED
RESERVED
RESERVED
Mindspeed Technologies™
ERROR
MERR
CERR
FERR
ISR5
006
—
Preliminary Information
RESERVED
FERR[12]
BERR[12]
FEBE[10]
CRC[10]
COFA[2]
RLOF[4]
COUNT
SEF[2]
ISR4
007
RESERVED
RESERVED
RESERVED
RESERVED
RFRAME
TFRAME
TIMER
ISR3
RMF
TMF
008
Table 8-7
TEMPTY
TDLERR
RNEAR
TNEAR
RFULL
TMSG
RMSG
TBOP
ISR2
DL1
009
summarizes the ISRs.
RBOP
ISR1
00A
DL2
—
—
—
—
—
—
—
Register Description
RESERVED
RESERVED
RESERVED
RESERVED
PSYNC
PATT
ISR0
00B
—
—
—
8
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