cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 51
cx29503
Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
1.CX29503.pdf
(388 pages)
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CX29503 Data Sheet
2.2
Figure 2-2. Mapper/Multiplexer (MUX) Block Diagram
29503-DSH-002-B
Interface
SI-Bus
DS3/E3 Serial
Interface
SI-Bus
Level
MUX
Top-
CX29503 Detailed Block Diagram
M13 Mode
RCVR_SEL
L3Map[1:0]
SI-Bus
Note: CK_SRC[1:0] are hardware pins
MUX
I/F
Figure 2-2
MUX blocks within the CX29503.
MUXing, and framing blocks, and the data paths through them.
L3Map[1:0]
2,3
STS-1 to
0
1
DS3/E3
Mapper
CK_SRC[1:0]
0x5000
0x01
0x6380
Register
Address
2,3
0,1
illustrates a detailed block diagram. There are three identical Mapper/
Mindspeed Technologies™
DS3/E3
Framer
M13/E13
DS1/E1
SONET/SDH
Unchannelized STS-1
Register
VC-11/VC-12
M13 Mode
Block
TUG-2/3 to
VT1.5/2.0
STS-1 to
Preliminary Information
MUX
1
0
M13/E13
Unchannelized DS3/E3
DEMUX
DS1/VC-11, and E1/VC-12
MUX
DS1/VT1.5, E1/VT2.0,
28xVT1.5/VC-11
21xVT2.0/VC-12
Tributary Mapper
Termination/
Generation
Figure 2-2
Overhead
RCVR_SEL
0
1
illustrates the major mapping,
Framers
28xDS1
21xE1
Processor Interface
To Host Processor
E-Bus Interface
(Optional)
E-Bus
and Status
Command
Processor
Time Slot
Interface
Module
Bus
SLICE 1
SLICE 2
SLICE 3
Functional Description
Overhead
Payload
TS-Bus
TS-Bus
100702_010
2
-
3
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