cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 274

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x54C3—DS2/E2 Framer 7 Transmit Control Register
Reset State
RSV_Bit
XmitAIS
XmitAutoRAI
XmitRAI
F-BitInv
M-BitInv
P-BitErr
0x5404—DS2/E2 Framer 1 Receive Control Register
0x5424—DS2/E2 Framer 2 Receive Control Register
0x5444—DS2/E2 Framer 3 Receive Control Register
0x5464—DS2/E2 Framer 4 Receive Control Register
0x5484—DS2/E2 Framer 5 Receive Control Register
0x54A4—DS2/E2 Framer 6 Receive Control Register
0x54C4—DS2/E2 Framer 7 Receive Control Register
Reset State
M-Bit ErrDis
8-144
—
—
7
7
0x00
In G.747 mode, the reserved bit (Bit 3 in Set II) is set to the value in the register:
• In E13 mode—National Use Bit Control
• In M13 mode—Unused
Transmit DS2/E2 AIS Towards the Line when set to 1
Automatically Transmit DS2/E2 RAI Towards the Line when set to 1
Transmit RAI Under Software Control when set to 1
Transmit F-Bit Inversion when set to 1—A single F-bit will be inverted at the next available
opportunity. After the error has been inserted, this bit will be cleared to 0 by hardware.
Transmit M-Bit Inversion when set to 1—A single M-bit will be inverted at the next available
opportunity. After the error has been inserted, this bit will be cleared to 0 by hardware.
Transmit Parity Bit Error when set to 1—A single parity bit error will be inserted at the next
available opportunity. After the error has been inserted, this bit will be cleared to 0 by
hardware. This bit is only applicable to G.747 mode.
0x00
Disable M-Bit Error Condition—When set to 1, the M-bit error condition is disabled in the
definition of OOF indication. This applies only to M13 mode.
P-BitErr
—
6
6
M-BitInv
—
5
5
Mindspeed Technologies™
F-BitInv
Preliminary Information
—
4
4
XmitRAI
InsAIS
3
3
XmitAuto
FrcRefr
RAI
2
2
Sel F-BitRatio
XmitAIS
1
1
CX29503 Data Sheet
29503-DSH-002-B
M-Bit ErrDis
RSV_Bit
0
0