cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 264

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x524C—Receive Data Link Message Byte
Value after reset:
Direction:
Value after enable:
RxDLMsg[7:0]
Table 8-48. Register Definitions (RxGoodBlk Set)
Table 8-49. Register Definition (RxGoodBlk Cleared)
8-134
RxDLMsg[7]
RxDLMsg[7]
RxDLMsg[7]
type select
Undefined
7
RxDLMsg[6]
RxDLMsg[6]
RxDLMsg[6]
Undefined
length[6]
Undefined
Read only
Undefined
Receive Data Link Message Byte—This register is used to read the content of the Receive
Data Link FIFO. Issuing a receive FIFO read is done by addressing this register, which results
in putting the byte read from the FIFO on the microprocessor data bus. The type of this
register’s content (status or data) is defined by the StatByte bit in the Receive Data Link Status
register.
The receive order of bits from the line is the RxDLMsg[0] bit is received first and the
RxDLMsg[7] bit is received last from the line. When this register contains data, it can be any
combination of 1s and 0s. When this register contains a status, it defines the status of the
following data block, where the RxDLMsg[7] bit defines the block’s type (complete or partial)
for a good block or undefined for an errored block. The other 7 bits are used as a length field
or error indications.
When RxGoodBlk is set,
for a complete message, cleared for a partial message.
When RxGoodBlk is cleared,
the content of the status register in an incorrect end-of-message state and details the different
error indications that can be set.
The error indications are as follows:
6
• Abort—When an abort sequence is detected, the message is terminated and the bit set.
• OVR—When an overrun error happens (the FIFO buffer is full and a new byte was
• AlignErr—When the number of bits in the message is indivisible by 8 (alignment
• BadFCS—When there is a mismatch between the calculated and the received FCS,
received), the message is terminated and the bit set.
error), the message is terminated and the bit set.
the message is terminated and the bit set. Only one error type out of the following list
is set according to the priority: OVR, Abort, AlignErr, or BadFCS (highest to lowest).
NOTE:
RxDLMsg[5]
RxDLMsg[5]
RxDLMsg[5]
Undefined
length[5]
5
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The length of the following block is always considered 0, and only 1 indication can be
set at a time.
Table 8-48
RxDLMsg[4]
RxDLMsg[4]
RxDLMsg[4]
Undefined
length[4]
Preliminary Information
Table 8-49
4
lists the structure of the status byte. RxDLMsg[7] is set
RxDLMsg[3]
RxDLMsg[3]
RxDLMsg[3]
shows the structure of the status byte. It illustrates
length[3]
Abort
3
RxDLMsg[2]
RxDLMsg[2]
RxDLMsg[2]
length[2]
OVR
2
RxDLMsg[1]
RxDLMsg[1]
RxDLMsg[1]
length[1]
AlignErr
1
CX29503 Data Sheet
29503-DSH-002-B
RxDLMsg[0]
RxDLMsg[0]
RxDLMsg[0]
length[0]
BadFCS
0