cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 299

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cx29503

Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
CX29503 Data Sheet
8.5.4.1
0x6000—Transmit SI-Bus Interrupt Enable
This interrupt register is at Level 1 in the SONET/SDH transmit interrupt hierarchy (see
corresponding Level 3 interrupt is the Transmit General interrupt in the Transmit Channel Status register
[addr: 0FF].
Reset State
EnTxStartErr
0x6001—Transmit SI-Bus Status
This register is a clear-on-read-type.
Reset State
TxStartErr
0x6004—BIP2 Error Pattern (Used for Diagnostics)
Reset State
ErrPat[7:6]
ErrPat[5:0]
29503-DSH-002-B
ErrPat[7]
7
7
7
ErrPat[6]
0x00
Transmit Start Error Status Interrupt Enable (1 = enable)
0x00
Transmit Start Signal Changed Phase—This status shows that an event has occurred since the
register was last read.
0x00
Error Pattern—This pattern is used to insert errors in the BIP2 field. This error pattern is
inserted on the VT path or paths that have the BIP2ErrIns bit in the VT# Transmit Overhead
Control 1 register (see
Not used for the CX29503.
6
6
6
SONET/SDH Top Level Transmitter Control
ErrPat[5]
5
5
5
Mindspeed Technologies™
Section
ErrPat[4]
Preliminary Information
4
4
8.6.1) enabled.
4
ErrPat[3]
3
3
3
ErrPat[2]
2
2
2
ErrPat[1]
Figure
1
1
1
v
8-6). The
Register Description
EnTxStartErr
TxStartErr
ErrPat[0]
0
0
0
8
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