LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 103

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 103. Register overview: I/O configuration (base address 0x4004 4000)
UM10398
User manual
Name
IOCON_PIO2_6
-
IOCON_PIO2_0
IOCON_RESET_PIO0_0
IOCON_PIO0_1
IOCON_PIO1_8
IOCON_SSEL1_LOC
IOCON_PIO0_2
IOCON_PIO2_7
IOCON_PIO2_8
IOCON_PIO2_1
IOCON_PIO0_3
IOCON_PIO0_4
IOCON_PIO0_5
IOCON_PIO1_9
IOCON_PIO3_4
IOCON_PIO2_4
IOCON_PIO2_5
IOCON_PIO3_5
IOCON_PIO0_6
Some input functions (SCK0, DSR, DCD, RI, SSEL1, CT16B0_CAP0, SCK1, MISO1,
MOSI1, CT32B0_CAP0, and RXD) are multiplexed to several physical pins. The
IOCON_LOC registers select the pin location for each of these functions.
Remark: The IOCON registers are listed in order of their memory locations in
which correspond to the order of their physical pin numbers in the LQFP48 package
starting at the upper left corner with pin 1 (PIO2_6). See
registers ordered by port number.
The IOCON location registers are used to select a physical pin for multiplexed functions.
Remark: Note that once the pin location has been selected, the function still must be
configured in the corresponding IOCON registers for the function to be usable on that pin.
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
0x018
Address
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
Rev. 12 — 24 September 2012
Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)
SSEL1 pin location select register
Description
I/O configuration for pin PIO2_6/
CT32B0_MAT1
Reserved
I/O configuration for pin
PIO2_0/DTR/SSEL1
I/O configuration for pin RESET/PIO0_0 0xD0
I/O configuration for pin
PIO0_1/CLKOUT/CT32B0_MAT2
I/O configuration for pin
PIO1_8/CT16B1_CAP0
I/O configuration for pin
PIO0_2/SSEL0/CT16B0_CAP0
I/O configuration for pin PIO2_7/
CT32B0_MAT2/RXD
I/O configuration for pin PIO2_8/
CT32B0_MAT3/TXD
I/O configuration for pin
PIO2_1/DSR/SCK1
I/O configuration for pin PIO0_3
I/O configuration for pin PIO0_4/SCL
I/O configuration for pin PIO0_5/SDA
I/O configuration for pin
PIO1_9/CT16B1_MAT0/ MOSI1
I/O configuration for pin PIO3_4/
CT16B0_CAP1/RXD
I/O configuration for pin PIO2_4/
CT16B1_MAT1/ SSEL1
I/O configuration for pin PIO2_5/
CT32B0_MAT0
I/O configuration for pin PIO3_5/
CT16B1_CAP1/TXD
I/O configuration for pin PIO0_6/SCK0
Table 104
Reset
value
0xD0
-
0xD0
0xD0
0xD0
0x0
0xD0
0xD0
0xD0
0xD0
0xD0
0x00
0x00
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
for a listing of IOCON
UM10398
© NXP B.V. 2012. All rights reserved.
Reference
Table 105
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Table 106
Table 107
Table 105
Table 109
Table 151
Table 110
Table 111
Table 112
Table 113
Table 114
Table 115
Table 116
Table 117
Table 118
Table 119
Table 120
Table 121
Table 122
Table
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