LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 484

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.5.5.2 Operation
28.5.5.5.3 Restrictions
28.5.5.5.4 Condition flags
28.5.5.5.5 Example
28.5.5.6.1 Syntax
28.5.5.6 MULS
MVNS Rd, Rm
where:
The MOV instruction copies the value of Rm into Rd.
The MOVS instruction performs the same operation as the MOV instruction, but also
updates the N and Z flags.
The MVNS instruction takes the value of Rm, performs a bitwise logical negate operation
on the value, and places the result into Rd.
In these instructions, Rd, and Rm must only specify R0-R7.
When Rd is the PC in a MOV instruction:
Remark: Though it is possible to use MOV as a branch instruction, ARM strongly
recommends the use of a BX or BLX instruction to branch for software portability.
If S is specified, these instructions:
Multiply using 32-bit operands, and producing a 32-bit result.
MULS Rd, Rn, Rm
•
•
•
•
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see
Rd is the destination register.
Rm is a register.
imm is any value in the range 0-255.
MOVS R0, #0x000B
Bit[0] of the result is discarded.
A branch occurs to the address created by forcing bit[0] of the result to 0. The T-bit
remains unmodified.
update the N and Z flags according to the result
do not affect the C or V flags.
MOVS R1, #0x0
MOV R10, R12
MOVS R3, #23
MOV R8, SP
MVNS R2, R0
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
; Write value of 0x000B to R0, flags get updated
Rev. 12 — 24 September 2012
; Write value of stack pointer to R8
; Write inverse of R0 to the R2 and update flags
; Write value of 23 to R3
; Write value in R12 to R10, flags are not updated
; Write value of zero to R1, flags are updated
Section
28–28.5.3.6.
UM10398
© NXP B.V. 2012. All rights reserved.
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