LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 281

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 246. CAN status register (CANSTAT, address 0x4005 0004) bit description
UM10398
User manual
Bit
2:0
3
4
5
Symbol
LEC
TXOK
RXOK
EPASS
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0
1
0
1
0
1
Description
Last error code
Type of the last error to occur on the CAN bus.The LEC field holds a
code which indicates the type of the last error to occur on the CAN bus.
This field will be cleared to ‘0’ when a message has been transferred
(reception or transmission) without error. The unused code ‘111’ may be
written by the CPU to check for updates.
No error.
Stuff error: More than 5 equal bits in a sequence have occurred in a
part of a received message where this is not allowed.
Form error: A fixed format part of a received frame has the wrong
format.
AckError: The message this CAN core transmitted was not
acknowledged.
Bit1Error: During the transmission of a message (with the exception of
the arbitration field), the device wanted to send a HIGH/recessive level
(bit of logical value ‘1’), but the monitored bus value was
LOW/dominant.
Bit0Error: During the transmission of a message (or acknowledge bit,
or active error flag, or overload flag), the device wanted to send a
LOW/dominant level (data or identifier bit logical value ‘0’), but the
monitored Bus value was HIGH/recessive. During busoff recovery this
status is set each time a sequence of 11 HIGH/recessive bits has been
monitored. This enables the CPU to monitor the proceeding of the
busoff recovery sequence (indicating the bus is not stuck at
LOW/dominant or continuously disturbed).
CRCError: The CRC checksum was incorrect in the message received.
Unused: No CAN bus event was detected (written by the CPU).
Transmitted a message successfully
This bit must be reset by the CPU. It is never reset by the CAN
controller.
Since this bit was last reset by the CPU, no message has been
successfully transmitted.
Since this bit was last reset by the CPU, a message has been
successfully transmitted (error free and acknowledged by at least one
other node).
Received a message successfully
This bit must be reset by the CPU. It is never reset by the CAN
controller.
Since this bit was last reset by the CPU, no message has been
successfully received.
Since this bit was last set to zero by the CPU, a message has been
successfully received independent of the result of acceptance filtering.
Error passive
The CAN controller is in the error active state.
The CAN controller is in the error passive state as defined in the CAN
2.0 specification.
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
UM10398
Reset
value
000
0
0
0
© NXP B.V. 2012. All rights reserved.
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Access
R/W
R/W
R/W
RO