LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 45

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.9.2.2 Programming Sleep mode
3.9.2.3 Wake-up from Sleep mode
3.9.3.1 Power configuration in Deep-sleep mode
3.9.3.2 Programming Deep-sleep mode
3.9.3 Deep-sleep mode
The following steps must be performed to enter Sleep mode:
Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the
processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns
to its original power configuration defined by the contents of the PDRUNCFG and the
SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default
configuration in Active mode.
In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All
analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,
which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG
register.
Deep-sleep mode eliminates all power used by the flash and analog peripherals and all
dynamic power used by the processor itself, memory systems and their related
controllers, and internal buses. The processor state and registers, peripheral registers,
and internal SRAM values are maintained, and the logic levels of the pins remain static.
Power consumption in Deep-sleep mode is determined by the Deep-sleep power
configuration setting in the PDSLEEPCFG
The following steps must be performed to enter Deep-sleep mode:
1. The DPDEN bit in the PCON register must be set to zero
2. The SLEEPDEEP bit in the ARM Cortex-M0 SCR register must be set to zero, see
3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction.
1. The DPDEN bit in the PCON register must be set to zero
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The system clock frequency remains the same as in Active mode, but the processor is
not clocked.
Analog and digital peripherals are selected as in Active mode.
(Table
The only clock source available in Deep-sleep mode is the watchdog oscillator. The
watchdog oscillator can be left running in Deep-sleep mode if required for
timer-controlled wake-up (see
system oscillator) and the system PLL are shut down. The watchdog oscillator analog
output frequency must be set to the lowest value of its analog clock output (bits
FREQSEL in the WDTOSCCTRL = 0001, see
The BOD circuit can be left running in Deep-sleep mode if required by the application.
If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer or
one of the general-purpose timers should be enabled in SYSAHBCLKCTRL register
to minimize power consumption.
452).
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Section
3.10.3). All other clock sources (the IRC and
(Table
41) register:
Table
13).
(Table
(Table
49).
49).
UM10398
© NXP B.V. 2012. All rights reserved.
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