LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 250

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.10.1 Master Transmitter mode
Table 233. Abbreviations used to describe an I
In
The numbers in the circles show the status code held in the STAT register. At these points,
a service routine must be executed to continue or complete the serial transfer. These
service routines are not critical since the serial transfer is suspended until the serial
interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in STAT is used to branch to the
appropriate service routine. For each status code, the required software action and details
of the following serial transfer are given in tables from
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(see
initialized as follows:
Table 234. I2C0CONSET used to initialize Master Transmitter mode
The I
to logic 1 to enable the I
its own slave address or the General Call address in the event of another device
becoming master of the bus. In other words, if AA is reset, the I
slave mode. STA, STO, and SI must be reset.
Abbreviation
S
SLA
R
W
A
A
Data
P
Bit
Symbol
Value
Figure 53
Figure
2
C rate must also be configured in the SCLL and SCLH registers. I2EN must be set
7
-
-
53). Before the master transmitter mode can be entered, I2CON must be
to
Figure
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
6
I2EN
1
57, circles are used to indicate when the serial interrupt flag is set.
Explanation
START Condition
7-bit slave address
Read bit (HIGH level at SDA)
Write bit (LOW level at SDA)
Acknowledge bit (LOW level at SDA)
Not acknowledge bit (HIGH level at SDA)
8-bit data byte
STOP condition
2
C block. If the AA bit is reset, the I
5
STA
0
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
4
STO
0
2
C operation
3
SI
0
Table 235
2
C block will not acknowledge
2
AA
x
2
C interface cannot enter
to
Table
UM10398
1
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© NXP B.V. 2012. All rights reserved.
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