LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 394

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
23.7.2 Watchdog Timer Constant register (WDTC - 0x4000 4004)
23.7.3 Watchdog Feed register (WDFEED - 0x4000 4008)
WDINT The Watchdog interrupt flag is set when the Watchdog times out. This flag is
cleared when any reset occurs. Once the watchdog interrupt is serviced, it can be
disabled in the NVIC or the watchdog interrupt request will be generated indefinitely. The
intent of the watchdog interrupt is to allow debugging watchdog activity without resetting
the device when the watchdog overflows.
Watchdog reset or interrupt will occur any time the watchdog is running and has an
operating clock source. Any clock source works in Sleep mode, and if a watchdog
interrupt occurs in Sleep mode, it will wake up the device.
Table 352. Watchdog operating modes selection
The WDTC register determines the time-out value. Every time a feed sequence occurs
the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB
set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the
WDTC. Thus the minimum time-out interval is T
Table 353. Watchdog Constant register (WDTC - address 0x4000 4004) bit description
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.
The reset will be generated during the second PCLK following an incorrect access to a
Watchdog register during a feed sequence.
WDEN
0
1
1
Bit
23:0
31:25
Symbol
Count
-
WDRESET
X (0 or 1)
0
1
All information provided in this document is subject to legal disclaimers.
Description
Watchdog time-out interval.
Reserved
Rev. 12 — 24 September 2012
Mode of Operation
Debug/Operate without the Watchdog running.
Watchdog interrupt mode: debug with the Watchdog interrupt but no
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will set the
WDINT flag and the Watchdog interrupt request will be generated.
Remark: In interrupt mode, check the WDINT flag. If this flag is set,
the interrupt is true and can be serviced by the interrupt routine. If this
flag is not set, the interrupt should be ignored.
Watchdog reset mode: operate with the Watchdog interrupt and
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will reset
the microcontroller. Although the Watchdog interrupt is also enabled
in this case (WDEN = 1) it will not be recognized since the watchdog
reset will clear the WDINT flag.
Chapter 23: LPC111x/LPC11Cxx WatchDog Timer (WDT)
WDCLK
 256  4.
UM10398
© NXP B.V. 2012. All rights reserved.
Reset Value
0x0000 00FF
-
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