LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 378

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
21.7.11 Count Control Register (TMR32B0CTCR and TMR32B1TCR)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs, and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one half of the
PCLK clock. Consequently, duration of the HIGH/LOW levels on the same CAP input in
this case can not be shorter than 1/(2  PCLK).
Bits 7:4 of this register are used to enable and configure the capture-clears-timer feature.
This feature allows for a designated edge on a particular CAP input to reset the timer to all
zeros. Using this mechanism to clear the timer on the leading edge of an input pulse and
performing a capture on the trailing edge permits direct pulse-width measurement using a
single capture input without the need to perform a subtraction operation in software.
Table 340: Count Control Register (TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR
Bit
1:0
3:2
4
Symbol
CTM
CIS
ENCC
- address 0x4001 8070) bit description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Rev. 12 — 24 September 2012
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
Description
Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or
clear PC and increment Timer Counter (TC).
Timer Mode: every rising PCLK edge
Timer Mode: every rising PCLK edge
Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
Count Input Select. When bits 1:0 in this register are not 00,
these bits select which CAP pin is sampled for clocking:
CT32Bn_CAP0
CT32Bn_CAP1
Reserved
Reserved
Note: If Counter mode is selected in the TnCTCR, the 3 bits
for that input in the Capture Control Register (TnCCR) must
be programmed as 000.
Setting this bit to one enables clearing of the timer and the
prescaler when the capture-edge event specified in bits 7:5
occurs.
UM10398
© NXP B.V. 2012. All rights reserved.
378 of 538
Reset
value
00
00
0