LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 388

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
22.7.3 Watchdog Feed register
22.7.4 Watchdog Timer Value register
22.7.5 Watchdog Timer Warning Interrupt register
Table 345: Watchdog Timer Constant register (WDTC - 0x4000 4004) bit description
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled,
and sets the WDTOF flag. The reset will be generated during the second PCLK following
an incorrect access to a Watchdog register during a feed sequence.
Table 346: Watchdog Feed register (WDFEED - 0x4000 4008) bit description
The WDTV register is used to read the current value of Watchdog timer counter.
When reading the value of the 24-bit counter, the lock and synchronization procedure
takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the
actual value of the timer when it's being read by the CPU.
Table 347: Watchdog Timer Value register (WDTV - 0x4000 400C) bit description
The WDWARNINT register determines the watchdog timer counter value that will
generate a watchdog interrupt. When the watchdog timer counter matches the value
defined by WDWARNINT, an interrupt will be generated after the subsequent WDCLK.
A match of the watchdog timer counter to WDWARNINT occurs when the bottom 10 bits
of the counter have the same value as the 10 bits of WARNINT, and the remaining upper
bits of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts
(4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. If WARNINT
is set to 0, the interrupt will occur at the same time as the watchdog event.
Bit
23:0
31:24
Bit
7:0
31:8
Bit
23:0
31:24
Symbol
Count
-
Symbol
Feed
-
Symbol
Count
-
All information provided in this document is subject to legal disclaimers.
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT)
Description
Watchdog time-out interval.
Reserved. Read value is undefined, only zero should be
written.
Description
Feed value should be 0xAA followed by 0x55.
Reserved
Description
Counter timer value.
Reserved. Read value is undefined, only zero should be
written.
Rev. 12 — 24 September 2012
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0x00 00FF
NA
Reset value
-
-
Reset value
0x00 00FF
-
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