LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 155

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 162. LPC11C24/C22 pin description table (LQFP48 package)
[1]
[2]
[3]
[4]
[5]
[6]
Table 163. LPC11D14 pin description table (LQFP100 package)
UM10398
User manual
Symbol
XTALIN
XTALOUT
V
Symbol
Microcontroller pins
PIO0_0 to PIO0_11
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3
PIO0_4/SCL
SS
5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
I
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.
5 V tolerant digital I/O pad without pull-up/pull-down resistors.
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
2
C-bus pads compliant with the I
Pin
6
7
5; 41
[7]
[7]
Pin
6
7
13
17
18
[1]
[3]
[3]
[3]
[4]
Type
I
O
I
Start
logic
input
yes
yes
yes
yes
yes
2
C-bus specification for I
Description
Input to the oscillator circuit and internal clock generator circuits. Input voltage must
not exceed 1.8 V.
Output from the oscillator amplifier.
Ground.
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
Type
I/O
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Reset
state
[1]
I; PU
-
I; PU
-
-
I; PU
-
-
I; PU
I; IA
-
2
C standard mode and I
Description
Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins
depends on the function selected through the IOCONFIG
register block.
RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address 0.
PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave Select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 — General purpose digital input/output pin.
PIO0_4 — General purpose digital input/output pin
(open-drain).
SCL — I
sink only if I
configuration register.
2
C-bus, open-drain clock input/output. High-current
2
C Fast-mode Plus is selected in the I/O
2
C Fast-mode Plus.
UM10398
© NXP B.V. 2012. All rights reserved.
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