LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 386

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
22.7 Register description
Table 342. Register overview: Watchdog timer (base address 0x4000 4000)
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UM10398
User manual
Name
WDMOD
WDTC
WDFEED
WDTV
WDWARNINT
WDWINDOW
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
22.7.1 Watchdog Mode register
Access Address
R/W
R/W
WO
RO
R/W
R/W
The Watchdog contains the registers shown in
The WDMOD register controls the operation of the Watchdog as per the combination of
WDEN and RESET bits. Note that a watchdog feed must be performed before any
changes to the WDMOD register take effect.
Table 343: Watchdog Mode register (WDMOD - 0x4000 4000) bit description
Bit
0
1
2
3
offset
0x000
0x004
0x008
0x00C
0x014
0x018
Symbol
WDEN
WDRESET
WDTOF
WDINT
Description
Watchdog mode register. This register contains the basic mode and
status of the Watchdog Timer.
Watchdog timer constant register. This register determines the
time-out value.
Watchdog feed sequence register. Writing 0xAA followed by 0x55 to
this register reloads the Watchdog timer with the value contained in
WDTC.
Watchdog timer value register. This register reads out the current
value of the Watchdog timer.
Watchdog Warning Interrupt compare value.
Watchdog Window compare value.
All information provided in this document is subject to legal disclaimers.
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT)
Value
0
1
0
1
Rev. 12 — 24 September 2012
Description
Watchdog enable bit. This bit is Set Only.
Remark: Setting this bit to one also locks the
watchdog clock source. Once the watchdog timer is
enabled, the watchdog timer clock source cannot be
changed. If the watchdog timer is needed in
Deep-sleep mode, the watchdog clock source must be
changed to the watchdog oscillator before setting this
bit to one.
The watchdog timer is stopped.
The watchdog timer is running.
Watchdog reset enable bit. This bit is Set Only.
A watchdog timeout will not cause a chip reset.
A watchdog timeout will cause a chip reset.
Watchdog time-out flag. Set when the watchdog timer
times out, by a feed error, or by events associated with
WDPROTECT, cleared by software. Causes a chip
reset if WDRESET = 1.
Watchdog interrupt flag. Set when the timer reaches
the value in WDWARNINT. Cleared by software.
Table
342.
UM10398
© NXP B.V. 2012. All rights reserved.
0
Reset value
0
0xFF
-
0xFF
0xFF FFFF
Reset
value
0
0
0 (Only
after
external
reset)
0
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