LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 438

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
26.10 Flash signature generation
UM10398
User manual
26.10.1.1 Signature generation address and control registers
26.10.1 Register description for signature generation
The flash module contains a built-in signature generator. This generator can produce a
128-bit signature from a range of flash memory. A typical usage is to verify the flashed
contents against a calculated signature (e.g. during programming).
The address range for generating a signature must be aligned on flash-word boundaries,
i.e. 128-bit boundaries. Once started, signature generation completes independently.
While signature generation is in progress, the flash memory cannot be accessed for other
purposes, and an attempted read will cause a wait state to be asserted until signature
generation is complete. Code outside of the flash (e.g. internal RAM) can be executed
during signature generation. This can include interrupt services, if the interrupt vector
table is re-mapped to memory other than the flash memory. The code that initiates
signature generation should also be placed outside of the flash memory.
Table 408. Register overview: FMC (base address 0x4003 C000)
These registers control automatic signature generation. A signature can be generated for
any part of the flash memory contents. The address range to be used for generation is
defined by writing the start address to the signature start address register (FMSSTART)
and the stop address to the signature stop address register (FMSSTOP. The start and
stop addresses must be aligned to 128-bit boundaries and can be derived by dividing the
byte address by 16.
Signature generation is started by setting the SIG_START bit in the FMSSTOP register.
Setting the SIG_START bit is typically combined with the signature stop address in a
single write.
Table 409
registers respectively.
Name
FMSSTART
FMSSTOP
FMSW0
FMSW1
FMSW2
FMSW3
FMSTAT
FMSTATCLR W
and
Access Address
R/W
R/W
R
R
R
R
R
Table 410
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
0x020
0x024
offset
0x02C
0x030
0x034
0x038
0xFE0
0xFE8
Chapter 26: LPC111x/LPC11Cxx Flash programming firmware
show the bit assignments in the FMSSTART and FMSSTOP
Description
Signature start address register
Signature stop-address register
Word 0 [31:0]
Word 1 [63:32]
Word 2 [95:64]
Word 3 [127:96]
Signature generation status register
Signature generation status clear
register
UM10398
Reset
value
0
0
-
-
-
-
0
-
© NXP B.V. 2012. All rights reserved.
Reference
Section 26.
10.1.3
Section 26.
10.1.4
Table 409
Table 410
Table 411
Table 412
Table 413
Table 414
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