LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 506

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.6.3.7.1 System Handler Priority Register 2
28.6.3.6 Configuration and Control Register
28.6.3.7 System Handler Priority Registers
The CCR is a read-only register and indicates some aspects of the behavior of the
Cortex-M0 processor. See the register summary in
The bit assignments are:
Table 453. CCR bit assignments
The SHPR2-SHPR3 registers set the priority level, 0 to 3, of the exception handlers that
have configurable priority.
SHPR2-SHPR3 are word accessible. See the register summary in
attributes.
To access to the system exception priority level using CMSIS, use the following CMSIS
functions:
The input parameter IRQn is the IRQ number, see
The system fault handlers, and the priority field and register for each handler are:
Table 454. System fault handler priority fields
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field,
and bits[5:0] read as zero and ignore writes.
The bit assignments are:
Bits
[31:10]
[9]
[8:4]
[3]
[2:0]
Handler
SVCall
PendSV
SysTick
•
•
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Name
-
STKALIGN
-
UNALIGN_TRP
-
Field
PRI_11
PRI_14
PRI_15
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Function
Reserved.
Always reads as one, indicates 8-byte stack alignment on
exception entry.
On exception entry, the processor uses bit[9] of the stacked PSR
to indicate the stack alignment. On return from the exception it
uses this stacked bit to restore the correct stack alignment.
Reserved.
Always reads as one, indicates that all unaligned accesses
generate a HardFault.
Reserved.
Register description
Section 28–28.6.3.7.1
Section 28–28.6.3.7.2
Table 28–427
Table 28–448
for more information.
for the CCR attributes.
Table 28–448
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