LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 220

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
14.6.2 SPI/SSP0 Control Register 1
Table 208: SPI/SSP Control Register 0 (SSP0CR0 - address 0x4004 0000, SSP1CR0 - address
This register controls certain aspects of the operation of the SPI/SSP controller.
Bit
3:0
5:4
6
7
15:8
31:16 -
Symbol Value
DSS
FRF
CPOL
CPHA
SCR
0x4005 8000) bit description
All information provided in this document is subject to legal disclaimers.
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x0
0x1
0x2
0x3
0
1
0
1
-
Rev. 12 — 24 September 2012
Description
Data Size Select. This field controls the number of bits
transferred in each frame. Values 0000-0010 are not
supported and should not be used.
4-bit transfer
5-bit transfer
6-bit transfer
7-bit transfer
8-bit transfer
9-bit transfer
10-bit transfer
11-bit transfer
12-bit transfer
13-bit transfer
14-bit transfer
15-bit transfer
16-bit transfer
Frame Format.
SPI
TI
Microwire
This combination is not supported and should not be used.
Clock Out Polarity. This bit is only used in SPI mode.
SPI controller maintains the bus clock low between frames.
SPI controller maintains the bus clock high between frames.
Clock Out Phase. This bit is only used in SPI mode.
SPI controller captures serial data on the first clock transition
of the frame, that is, the transition away from the inter-frame
state of the clock line.
SPI controller captures serial data on the second clock
transition of the frame, that is, the transition back to the
inter-frame state of the clock line.
Serial Clock Rate. The number of prescaler output clocks per
bit on the bus, minus one. Given that CPSDVSR is the
prescale divider, and the APB clock PCLK clocks the
prescaler, the bit frequency is PCLK / (CPSDVSR  [SCR+1]).
Reserved
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
UM10398
© NXP B.V. 2012. All rights reserved.
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Reset
Value
0000
00
0
0x00
-
0