LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 236

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
I2EN should not be used to temporarily release the I
I
STA is the START flag. Setting this bit causes the I
transmit a START condition or transmit a Repeated START condition if it is already in
master mode.
When STA is 1 and the I
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition
after a delay of a half clock period of the internal clock generator. If the I
already in master mode and data has been transmitted or received, it transmits a
Repeated START condition. STA may be set at any time, including when the I
is in an addressed slave mode.
STA can be cleared by writing 1 to the STAC bit in the CONCLR register. When STA is 0,
no START condition or Repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I
interface is in master mode, and transmits a START condition thereafter. If the I
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
STO is the STOP flag. Setting this bit causes the I
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I
the STOP condition, STO is cleared automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to “not addressed” slave receiver mode. The STO flag is
cleared by hardware automatically.
SI is the I
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI
flag. SI must be reset by software, by writing a 1 to the SIC bit in the CONCLR register.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
2
1. The address in the Slave Address Register has been received.
2. The General Call address has been received while the General Call bit (GC) in the
3. A data byte has been received while the I
4. A data byte has been received while the I
C-bus status is lost. The AA flag should be used instead.
ADR register is set.
2
C Interrupt Flag. This bit is set when the I
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
2
C interface is not already in master mode, it enters master mode,
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
2
2
C is in the master receiver mode.
C is in the addressed slave receiver mode
2
2
C interface to transmit a STOP
C interface to enter master mode and
2
2
C-bus since, when I2EN is reset, the
C state changes. However, entering
2
C-bus. When the bus detects
UM10398
© NXP B.V. 2012. All rights reserved.
2
C interface is
2
C-bus if it the
2
C interface
2
C
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