LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 533

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
20.7
20.7.1
20.7.2
20.7.3
20.7.4
20.7.5
20.7.6
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.7.1
21.7.2
21.7.3
21.7.4
21.7.5
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT)
22.1
22.2
22.3
22.4
22.5
22.6
22.7
Chapter 23: LPC111x/LPC11Cxx WatchDog Timer (WDT)
23.1
UM10398
User manual
Register description . . . . . . . . . . . . . . . . . . . 355
How to read this chapter . . . . . . . . . . . . . . . . 368
Basic configuration . . . . . . . . . . . . . . . . . . . . 368
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 369
Register description . . . . . . . . . . . . . . . . . . . 369
How to read this chapter . . . . . . . . . . . . . . . . 383
Basic configuration . . . . . . . . . . . . . . . . . . . . 383
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 384
General description . . . . . . . . . . . . . . . . . . . . 384
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . 385
Register description . . . . . . . . . . . . . . . . . . . 386
How to read this chapter . . . . . . . . . . . . . . . . 391
Interrupt Register (TMR32B0IR and
TMR32B1IR). . . . . . . . . . . . . . . . . . . . . . . . . 357
Timer Control Register (TMR32B0TCR and
TMR32B1TCR) . . . . . . . . . . . . . . . . . . . . . . . 357
Timer Counter (TMR32B0TC - address
0x4001 4008 and TMR32B1TC - address
0x4001 8008) . . . . . . . . . . . . . . . . . . . . . . . . 358
Prescale Register (TMR32B0PR - address
0x4001 400C and TMR32B1PR - address
0x4001 800C) . . . . . . . . . . . . . . . . . . . . . . . . 358
Prescale Counter Register (TMR32B0PC -
address 0x4001 4010 and TMR32B1PC - address
0x4001 8010) . . . . . . . . . . . . . . . . . . . . . . . . 358
Match Control Register (TMR32B0MCR and
TMR32B1MCR) . . . . . . . . . . . . . . . . . . . . . . 359
Interrupt Register (TMR32B0IR and
TMR32B1IR). . . . . . . . . . . . . . . . . . . . . . . . . 372
Timer Control Register (TMR32B0TCR and
TMR32B1TCR) . . . . . . . . . . . . . . . . . . . . . . . 372
Timer Counter (TMR32B0TC - address
0x4001 4008 and TMR32B1TC - address
0x4001 8008) . . . . . . . . . . . . . . . . . . . . . . . . 372
Prescale Register (TMR32B0PR - address
0x4001 400C and TMR32B1PR - address
0x4001 800C) . . . . . . . . . . . . . . . . . . . . . . . . 373
Prescale Counter Register (TMR32B0PC -
address 0x4001 4010 and TMR32B1PC - address
0x4001 8010) . . . . . . . . . . . . . . . . . . . . . . . . 373
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
20.7.7
20.7.8
20.7.9
20.7.10
20.7.11
20.7.12
20.7.13
20.8
20.9
21.7.6
21.7.7
21.7.8
21.7.9
21.7.10
21.7.11
21.7.12
21.8
21.8.1
21.8.2
21.9
22.7.1
22.7.2
22.7.3
22.7.4
22.7.5
22.7.6
22.7.7
23.2
Example timer operation . . . . . . . . . . . . . . . 366
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Functional description . . . . . . . . . . . . . . . . . 380
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Basic configuration. . . . . . . . . . . . . . . . . . . . 391
Match Registers (TMR32B0MR0/1/2/3 -
addresses 0x4001 4018/1C/20/24 and
TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24) . . . . . . . . . . . . . . . . . . . . . . 360
Capture Control Register (TMR32B0CCR and
TMR32B1CCR) . . . . . . . . . . . . . . . . . . . . . . 360
Capture Register (TMR32B0CR0 - address
0x4001 402C and TMR32B1CR0 - address
0x4001 802C) . . . . . . . . . . . . . . . . . . . . . . . 361
External Match Register (TMR32B0EMR and
TMR32B1EMR) . . . . . . . . . . . . . . . . . . . . . . 361
Count Control Register (TMR32B0CTCR and
TMR32B1TCR) . . . . . . . . . . . . . . . . . . . . . . 363
PWM Control Register (TMR32B0PWMC and
TMR32B1PWMC) . . . . . . . . . . . . . . . . . . . . 364
Rules for single edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Match Control Register (TMR32B0MCR and
TMR32B1MCR) . . . . . . . . . . . . . . . . . . . . . . 373
Match Registers (TMR32B0MR0/1/2/3 -
addresses 0x4001 4018/1C/20/24 and
TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24) . . . . . . . . . . . . . . . . . . . . . . 374
Capture Control Register (TMR32B0CCR and
TMR32B1CCR) . . . . . . . . . . . . . . . . . . . . . . 375
Capture Register (TMR32B0CR0/1 - address
0x4001 402C/30 and TMR32B1CR0/1 - address
0x4001 802C/30) . . . . . . . . . . . . . . . . . . . . . 376
External Match Register (TMR32B0EMR and
TMR32B1EMR) . . . . . . . . . . . . . . . . . . . . . . 376
Count Control Register (TMR32B0CTCR and
TMR32B1TCR) . . . . . . . . . . . . . . . . . . . . . . 378
PWM Control Register (TMR32B0PWMC and
TMR32B1PWMC) . . . . . . . . . . . . . . . . . . . . 379
Example timer operation . . . . . . . . . . . . . . . 380
Rules for single edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Watchdog Mode register . . . . . . . . . . . . . . . 386
Watchdog Timer Constant register . . . . . . . 387
Watchdog Feed register . . . . . . . . . . . . . . . 388
Watchdog Timer Value register . . . . . . . . . . 388
Watchdog Timer Warning Interrupt register
Watchdog Timer Window register . . . . . . . . 389
Watchdog timing examples . . . . . . . . . . . . . 389
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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