LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 474

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.4.2.3 Restrictions
28.5.4.2.4 Condition flags
28.5.4.2.5 Examples
28.5.4.3.1 Syntax
28.5.4.3 LDR and STR, register offset
STR, STRB and STRH instructions store the word, least-significant byte or lower halfword
contained in the single register specified by Rt in to memory. The memory address to load
from or store to is the sum of the value in the register specified by either Rn or SP and the
immediate value imm.
In these instructions:
These instructions do not change the flags.
Load and Store with register offset.
LDR Rt, [Rn, Rm]
LDR<B|H> Rt, [Rn, Rm]
LDR<SB|SH> Rt, [Rn, Rm]
STR Rt, [Rn, Rm]
STR<B|H> Rt, [Rn, Rm]
where:
•
•
•
Rt is the register to load or store.
Rn is the register on which the memory address is based.
Rm is a register containing a value to be used as the offset.
LDR
Rt and Rn must only specify R0-R7.
imm must be between:
– 0 and 1020 and an integer multiple of four for LDR and STR
– 0 and 124 and an integer multiple of four for LDR and STR
– 0 and 62 and an integer multiple of two for LDRH and STRH
– 0 and 31 for LDRB and STRB.
The computed address must be divisible by the number of bytes in the transaction,
see
STR
using SP as the base register
using R0-R7 as the base register
Section
R4, [R7
R2, [R0,#const-struc] ; const-struc is an expression evaluating
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
28–28.5.3.4.
Rev. 12 — 24 September 2012
; to a constant in the range 0-1020.
; Loads R4 from the address in R7.
UM10398
© NXP B.V. 2012. All rights reserved.
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