LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 190

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

13.1 How to read this chapter
13.2 Basic configuration
13.3 Features
UM10398
User manual
The UART block is identical for all LPC111x, LPC11D14, and LPC11Cxx parts. The DSR,
DCD, and RI modem signals are fully pinned out on the LQFP48 packages only.
Note that for parts of the LPC1100 series (LPC111x/101/201/301), the UART pins must be
configured before the UART clock can be enabled. No enabling sequence requirement
exists for parts LPC11Cxx , parts in the LPC1100L and LPC1100XL series, and
LPC11D14.
The UART is configured using the following registers:
1. Pins: For the LPC111x/101/201/301 parts, the UART pins must be configured in the
2. Power: In the SYSAHBCLKCTRL register, set bit 12
3. Peripheral clock: Enable the UART peripheral clock by writing to the UARTCLKDIV
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UM10398
Chapter 13: LPC111x/LPC11Cxx UART
Rev. 12 — 24 September 2012
IOCONFIG register block
SYSAHBCLKCTRL register. For all other parts, no special enabling sequence is
required.
Remark: If the modem input pins are used, the modem function location must be also
selected in the UART location registers
register
16-byte receive and transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
Built-in baud rate generator.
UART allows for implementation of either software or hardware flow control.
RS-485/EIA-485 9-bit mode support with output enable.
Modem control.
(Table
All information provided in this document is subject to legal disclaimers.
23).
Rev. 12 — 24 September 2012
(Section
7.4) before the UART clocks can be enabled in the
(Section
7.4)
(Table
21).
© NXP B.V. 2012. All rights reserved.
User manual
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