LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 297

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
16.7 Functional description
UM10398
User manual
16.6.4.1 CAN clock divider register
16.7.2.1 Software initialization
16.6.4 CAN timing register
16.7.1 C_CAN controller state after reset
16.7.2 C_CAN operating modes
This register determines the CAN clock signal. The CAN_CLK is derived from the
peripheral clock PCLK divided by the values in this register.
Table 274. CAN clock divider register (CANCLKDIV, address 0x4005 0180) bit description
After a hardware reset, the registers hold the values described in
the busoff state is reset and the output CAN_TXD is set to recessive (HIGH). The value
0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The
CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM is undefined.
The software initialization is started by setting the bit INIT in the CAN Control Register,
either by software or by a hardware reset, or by entering the busoff state.
During software initialization (INIT bit is set), the following conditions are present:
To initialize the CAN controller, software has to set up the bit timing register and each
message object. If a message object is not needed, it is sufficient to set its MSGVAL bit to
not valid. Otherwise, the whole message object has to be initialized.
Bit
3:0
31:4
•
•
•
•
•
All message transfer from and to the CAN bus is stopped.
The status of the CAN output CAN_TXD is recessive (HIGH).
The EC counters are unchanged.
The configuration registers are unchanged.
Access to the bit timing register and the BRP extension register is enabled if the CCE
bit in the CAN control register is also set.
Symbol
CLKDIVVAL Clock divider value. CAN_CLK =
-
All information provided in this document is subject to legal disclaimers.
Description
PCLK/(CLKDIVVAL +1)
0000: CAN_CLK = PCLK divided by 1.
0001: CAN_CLK = PCLK divided by 2.
0010: CAN_CLK = PCLK divided by 3
0011: CAN_CLK = PCLK divided by 4.
...
1111: CAN_CLK = PCLK divided by 16.
reserved
Rev. 12 — 24 September 2012
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
Table
UM10398
© NXP B.V. 2012. All rights reserved.
244. Additionally,
Reset
value
0000
-
297 of 538
Access
R/W
-